1. Algorithm simulation effect

The system has been developed on two platforms, namely:

Vivado2019.2

Quartusii18.0+ModelSim-Altera 6.6d Starter Edition

The Vivado2019.2 simulation results are as follows:

The test results of Quartusii18.0+ModelSim-Altera 6.6d Starter Edition are as follows:

2. Algorithms involve an overview of theoretical knowledge

The time domain expressions of the B2PSK signal and the 2ASK signal are exactly the same in form, the only difference is the composition of the baseband signal s(t) of the two, one is composed of bipolar NRZ code, and the other is composed of unipolar NRZ code composition. Therefore, when calculating the power spectral density of the BPSK signal, the same method as that used to calculate the power spectral density of the 2ASK signal can also be used.
(1) When the bipolar baseband signals appear with equal probability (p=1/2), the power spectrum of the BPSK signal consists only of continuum spectrum. The power spectrum of BPSK signal consists of two parts, continuous spectrum and discrete spectrum. Among them, the continuous spectrum depends on the double-sided band spectrum after the linear modulation of the digital baseband signal s(t), while the discrete spectrum is determined by the carrier component.
(2) The continuum part of BPSK is basically the same as the continuum of 2ASK signal (there is only a constant factor difference). Therefore, the bandwidth and bandwidth utilization of the BPSK signal are also the same as those of the 2ASK signal.
In digital modulation, the spectral characteristics of BPSK (as will be seen later in 2DPSK) are very similar to 2ASK. Phase modulation, like frequency modulation, is essentially a nonlinear modulation. However, in digital phase modulation, since the phase change that characterizes information has only limited discrete values, the phase change can be attributed to an amplitude change. In this way, the digital amplitude modulation of the same linear modulation is connected with the digital modulation, so the digital phase modulation signal can be treated as a linear modulation signal. However, the above concept cannot be extended to all phase modulation signals.
BPSK (Binary Phase Shift Keying)-------Binary Phase Shift Keying. It is one of the conversion methods for converting analog signals into data values. It uses the complex number wave combination that deviates from the phase to express the information keying phase shifting method. In BPSK, a standard sine wave and a phase-reversed wave are used, and one of them is 0 and the other is 1, so that binary (1-bit) information can be transmitted and received at the same time.

Since the simplest keyed phase-shift method has strong anti-noise but poor transmission efficiency, QPSK using 4 phases and BPSK using 8 phases are often used.

A system for coherently demodulating a binary phase shift keying (BPSK) signal, which includes: a device for recovering a carrier signal (C) with a frequency of 2F from the BPSK signal; means for injecting the above-mentioned signal into an injection-locked oscillator (ILO) having a natural resonant frequency f↓[r] approximately equal to f, the injection-locked oscillator is provided for recovering Differential output (o↓[p], o↓[n]) signal of original carrier with (θ↓[e]-k)/2 phase shift, where θ = arcsin[(f↓[r]-r)/ αA↓[i]f], where α and k are parameters depending on the type of dominant nonlinearity in the injection-locked oscillator (ILO), and A↓[i] is the recovered carrier signal of frequency 2f and means for combining said differential output (o↓[p], o↓[n]) signal with a copy of said input BPSK signal to produce a demodulated signal (DEMOD).

3. Verilog core program

..............................................................
    
//调制端    
assign o_nz=(i_bits == 1'b1)?2'b01:2'b11;
    
wire[23:0]m_fir;
fir_compiler_0 uut (
  .aresetn(~i_rst),                        
  .aclk(i_clk),                               
  .s_axis_data_tvalid(1'b1),   
  .s_axis_data_tready(),  
  .s_axis_data_tdata({o_nz[1],o_nz[1],o_nz[1],o_nz[1],o_nz[1],o_nz[1],o_nz}),   
  .m_axis_data_tvalid(),   
  .m_axis_data_tdata(m_fir)    
);   

assign o_fir=m_fir[23:8]; 
    
wire[31:0]m_carrier;
dds_compiler_0 uut2(
  .aclk    (i_clk),                            
  .aresetn (~i_rst),                          
  .s_axis_config_tvalid(1'b1),   
  .s_axis_config_tdata(32'd100000000),    
  .m_axis_data_tvalid(),      
  .m_axis_data_tdata(m_carrier),        
  .m_axis_phase_tvalid(),   
  .m_axis_phase_tdata()      
);
assign o_carrier=m_carrier[15:0];    
    
    
always @(posedge i_clk or posedge i_rst)
begin
     if(i_rst)
     begin
     o_mod <= 32'd0;
     end
else begin
     o_mod <= $signed(o_carrier)*$signed(o_fir);
     end
end    
    
    
    
//解调端 ,不考虑载波同步
wire[31:0]m_carrier_local;
dds_compiler_0 uut3(
  .aclk    (i_clk),                            
  .aresetn (~i_rst),                          
  .s_axis_config_tvalid(1'b1),   
  .s_axis_config_tdata(32'd100000000),    
  .m_axis_data_tvalid(),      
  .m_axis_data_tdata(m_carrier_local),        
  .m_axis_phase_tvalid(),   
  .m_axis_phase_tdata()      
);
assign o_carrier_local=m_carrier_local[15:0];   
 
reg signed[31:0]tmps;
always @(posedge i_clk or posedge i_rst)
begin
     if(i_rst)
     begin
     tmps <= 32'd0;
     end
else begin
     tmps <= $signed(o_carrier_local)*$signed(o_mod[31:16]);
     end
end       
assign o_dw=tmps;

wire signed[31:0]tmps2;
fiter_rrc uut4(
.i_clk  (i_clk),
.i_rst  (i_rst),
.i_dat  (tmps[20:5]),
.o_demod(o_demod)
);
 
endmodule
00_001m

4. Complete algorithm code file

m Verilog implementation of FPGA-based BPSK modulation and demodulation communication system, including testbench, excluding carrier synchronization

1. Algorithm simulation effect

2. Algorithms involve an overview of theoretical knowledge

3. Verilog core program

4. Complete algorithm code file

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