m FPGA-based 8FSK modem system verilog implementation, including testbench test files

Table of contents

1. Algorithm simulation effect

2. Summary of theoretical knowledge involved in algorithms

3.Verilog core program

4. Obtain the complete algorithm code file

1. Algorithm simulation effect

The simulation results of vivado2019.2 are as follows:

Zoom in on the waveform and see the following effect:

2. Summary of theoretical knowledge involved in algorithms

8FSK (8-Frequency Shift Keying) is a commonly used digital modulation method that communicates by sending binary data on different frequencies. 8FSK is widely used in communication systems because of its high data transmission rate and strong anti-interference ability.

In 8FSK, each binary bit is sent on a specific frequency. The frequency of transmission changes according to the data bits transmitted. Specifically, the frequency of transmission is determined according to the value of the binary bits transmitted.

Specifically, 8FSK uses 8 different frequencies to represent 8 different binary bits. Frequencies f0 to f7 correspond to binary bits 000 to 111. Each frequency corresponds to a specific time interval, called the symbol time. Within one symbol time, data bits are sent. At the transmitting end, the input binary data is first divided into groups of two bits and then mapped to the corresponding frequency according to the following rules:

000 - f0
001 - f1
010 - f2
011 - f3
100 - f4
101 - f5
110 - f6
111 - f7

The above is a common mapping method, but other mapping methods can also be used.

At the receiving end, the 8FSK signal is received and demodulated to recover the original binary data. The demodulator needs to know the corresponding binary bits for each frequency in order to correctly recover the data. Demodulators can be implemented using various methods such as filters, spectrum analysis, etc.

The basic principle of 8FSK modulation can be expressed by mathematical formulas. Assuming that the input binary data is b(t) and the transmitted frequency is f(t), the FM signal s(t) can be expressed as:

s(t) = Re[b(t)exp(j2πf(t))]

Among them, Re represents the real part, j represents the imaginary unit, and π represents pi.

At the receiving end, the demodulator needs to demodulate the received signal to recover the original binary data. Demodulation can be achieved using various methods, such as envelope detection, synchronization detection, etc. The basic principle of envelope detection is to detect the envelope of the received signal to restore the original data. Its mathematical formula can be expressed as:

b(t) = Re[s(t)exp(-j2πf(t))]

8FSK modulation has the following advantages:

Higher transmission rates: Because multiple frequencies are used for transmission, higher transmission rates can be achieved.
Strong anti-interference ability: Due to the use of frequency offset keying, it has strong anti-interference ability.
Suitable for multipath propagation environment: Since different frequencies are used for transmission, it can be suitable for multipath propagation environment.
Simple implementation: Compared with other digital modulation methods, the implementation of 8FSK is relatively simple.

However, 8FSK modulation also has the following disadvantages:

Lower band utilization: Since multiple frequencies are used for transmission, the frequency band utilization is lower.

3.Verilog core program

`timescale 1ns / 1ps
//
 
//

module test_FSK;
 
reg i_clk;
reg i_rst;
reg[2:0]i_bits;
wire signed[15:0]o_carrier1;
wire signed[15:0]o_carrier2;
wire signed[15:0]o_carrier3;
wire signed[15:0]o_carrier4;
wire signed[15:0]o_carrier5;
wire signed[15:0]o_carrier6;
wire signed[15:0]o_carrier7;
wire signed[15:0]o_carrier8;
wire signed[31:0]o_de_fsk1;
wire signed[31:0]o_de_fsk2;
wire signed[31:0]o_de_fsk3;
wire signed[31:0]o_de_fsk4;
wire signed[31:0]o_de_fsk5;
wire signed[31:0]o_de_fsk6;
wire signed[31:0]o_de_fsk7;
wire signed[31:0]o_de_fsk8;
wire signed[15:0]o_fsk;
wire [2:0]o_bits;

FSK uut(
.i_clk(i_clk),
.i_rst(i_rst),
.i_bits(i_bits),
.o_carrier1(o_carrier1),
.o_carrier2(o_carrier2),
.o_carrier3(o_carrier3),
.o_carrier4(o_carrier4),
.o_carrier5(o_carrier5),
.o_carrier6(o_carrier6),
.o_carrier7(o_carrier7),
.o_carrier8(o_carrier8),
.o_fsk(o_fsk),
.o_de_fsk1(o_de_fsk1),
.o_de_fsk2(o_de_fsk2),
.o_de_fsk3(o_de_fsk3),
.o_de_fsk4(o_de_fsk4),
.o_de_fsk5(o_de_fsk5),
.o_de_fsk6(o_de_fsk6),
.o_de_fsk7(o_de_fsk7),
.o_de_fsk8(o_de_fsk8),
.o_bits(o_bits)
);

initial
begin
    i_clk = 1'b1;
    i_rst = 1'b1;
    #1000
    i_rst = 1'b0;
end
initial
begin
    i_bits= 3'b000;
    #3050
    repeat(100)
    begin
    #700
    i_bits= 3'b000;
    #900
    i_bits= 3'b011;
    #880
    i_bits= 3'b000;
    #900
    i_bits= 3'b001;
    #700
    i_bits= 3'b010;
    #800
    i_bits= 3'b100;
    #800
    i_bits= 3'b011;
    #1600
    i_bits= 3'b011;
    #1600
    i_bits= 3'b100;
    #600
    i_bits= 3'b110;
    #700
    i_bits= 3'b100;
    #600
    i_bits= 3'b101;
    #1600
    i_bits= 3'b111;
    #1800
    i_bits= 3'b010;
    #1400
    i_bits= 3'b01;
    #1400
    i_bits= 3'b101;
    #1400
    i_bits= 3'b100;
    
    #1900
    i_bits= 3'b101;
    #1700
    i_bits= 3'b101;
    #700
    i_bits= 3'b001;
    #1700
    i_bits= 3'b000;
    #1800
    i_bits= 3'b101;
    #1600
    i_bits= 3'b100;
    #1400
    i_bits= 3'b100;
    #1600
    i_bits= 3'b000;
    end
end



always #5 i_clk=~i_clk;

endmodule
00_048m