m FPGA-based 8FSK modem system verilog implementation, including testbench test files - Code World

m FPGA-based 8FSK modem system verilog implementation, including testbench test files

Language 2023-12-16 21:10:40 views: null

NoSuchKey

Guess you like

Origin blog.csdn.net/hlayumi1234567/article/details/133997470

m FPGA-based 8FSK modem system verilog implementation, including testbench test files

m FPGA-based 4FSK modem system verilog implementation, including testbench test files

m FPGA-based 8ASK modem system verilog implementation, including testbench test files

m FPGA-based 4ASK modem system verilog implementation, including testbench test files

m FPGA-based 8PSK modulation and demodulation system verilog implementation, including testbench test files

m Implementation of PAPR reduction technology in FPGA-based OFDM system, including testbench test files and MATLAB auxiliary testing

m Verilog implementation of FPGA-based BPSK modulation and demodulation communication system, including testbench, excluding carrier synchronization

m Verilog implementation of FPGA-based QPSK modulation and demodulation communication system, including testbench, excluding carrier synchronization

m Verilog implementation of FPGA-based interleaving and deinterleaving system, including testbench

m FPGA-based AGC adaptive gain control system verilog implementation, including testbench

m FPGA-based CRC cyclic redundancy check system verilog implementation, including testbench

m Verilog implementation of FPGA-based DQPSK modulation and demodulation communication system, including testbench, excluding carrier synchronization

m FPGA-based OFDM modulation and demodulation system verilog implementation, including IFFT, FFT and shaping filters, including testbench

m FPGA-based OFDM system verilog implementation, including IFFT, FFT, shaping filtering and CP addition and CP removal, including testbench

m FPGA-based data serial-to-parallel conversion system verilog implementation, including testbench, can configure the number of parallel

m FPGA-based Gaussian white noise channel simulation system verilog implementation, including testbench, can be configured with different SNR and frequency offset

m FPGA-based FOC controller verilog implementation, including CLARK, PARK, PID and SVPWM, including testbench

m FPGA-based basic OFDM modulation and demodulation verilog implementation, including IFFT and FFT, including testbench

m FPGA-based communication data frame scrambling and descrambling verilog implementation, including testbench

m FPGA-based 256QAM modulation signal generation module verilog implementation, including testbench

m FPGA-based 1024QAM modulation signal generation module verilog implementation, including testbench

m FPGA-based QPSK soft demodulation verilog implementation, including testbench and MATLAB auxiliary verification program

m FPGA-based 16QAM soft demodulation verilog implementation, including testbench

m FPGA-based LDPC minimum sum decoding algorithm verilog implementation, including testbench and matlab auxiliary verification program

m FPGA-based implementation of phase estimation and compensation algorithm for QPSK modulated signal with phase deviation in verilog, including testbench

m FPGA-based verilog implementation of phase estimation and compensation algorithm for 64QAM modulated signal with phase deviation, including testbench

m FPGA-based 256-point FFT Fourier transform verilog implementation, including testbench, without using IP core

m FPGA-based implementation of costas ring carrier synchronization verilog, including testbench, which can modify the frequency offset

Lorenz chaos system verilog development based on FPGA, including testbench and matlab auxiliary test programs

m Data frame detection based on PN sequence, frame synchronization verilog implementation, including testbench

Recommended

Ranking

css + html achieve 3D photo wall

Python Concise Guide: Novice will learn object-oriented []

ES6 inheritance (review prototype chain inheritance)

"A long article teaches you how to use appium in all aspects"

The third individual work - prototyping

HTML entity characters

Django (three) RESTFul of Django

Analysis of U disk file system (take FAT32 as an example)

Commonly used image drawing online experimental level - Level 5: Pie chart drawing

java programming design ideas

Daily

More

2025-05-02(0)

2025-05-01(0)

2025-04-30(0)

2025-04-29(0)

2025-04-28(0)

2025-04-27(0)

2025-04-26(0)

2025-04-25(0)

2025-04-24(0)

2025-04-23(0)