Table of contents
1. Algorithm simulation effect
2. Summary of theoretical knowledge involved in algorithms
2.2 Design and implementation of OFDM system based on FPGA
2.2.1IFFT/FFT module design and implementation
2.2.2 Design and implementation of shaping filter module
2.2.3 Design and implementation of adding CP and removing CP module
4. Obtain the complete algorithm code file
1. Algorithm simulation effect
The simulation results of vivado2019.2 are as follows:
CP added, deleted effect:
System RTL structure diagram:
2. Summary of theoretical knowledge involved in algorithms
Orthogonal Frequency Division Multiplexing (OFDM) is an efficient wireless communication technology that has been widely used in the field of wireless communications. The main advantage of OFDM technology is that it can effectively resist multipath effects and frequency selective fading, thereby improving the performance and reliability of wireless communication systems. However, the implementation complexity of OFDM system is high and requires efficient digital signal processing technology. Field Programmable Gate Array (FPGA), as a programmable logic device, has a high degree of flexibility and parallel processing capabilities, and is very suitable for implementing complex digital signal processing algorithms.
2.1 OFDM principle
OFDM is a multi-carrier modulation technology. Its basic principle is to divide high-speed data streams into several low-speed data streams, and then modulate them onto a set of orthogonal sub-carriers for transmission. At the receiving end, the original high-speed data stream can be recovered by demodulating each subcarrier. Specifically, assuming that the number of subcarriers in the OFDM system is N and the symbol period is Ts, the frequency of the k-th subcarrier is fk=k/Ts. Within one symbol period, OFDM symbols can be expressed as:
s(t)=∑[n=0,N-1]X[n]exp(j2πnft)（1）
Where, X[n] is the modulation symbol on the n-th subcarrier, which can be the symbol of QPSK, QAM and other modulation methods. exp(j2πnft) is the phase rotation factor of the nth subcarrier.
At the receiving end, by demodulating the received OFDM symbols, the modulation symbols on each subcarrier can be recovered. Specifically, the demodulation symbol on the k-th subcarrier can be expressed as:
Y[k]=∫[t=0,Ts]r(t)exp(-j2πkft)dt（2）
Where, r(t) is the received OFDM symbol. By performing parallel-to-serial conversion and decoding of the demodulated symbols on all subcarriers, the original high-speed data stream can be recovered.
2.2 Design and implementation of OFDM system based on FPGA
The FPGA-based OFDM system mainly consists of the following parts: IFFT/FFT module, shaping filter module, CP addition and CP removal module, and control module. Among them, the IFFT/FFT module is used to realize the modulation and demodulation of OFDM symbols; the shaping filter module is used to shape and filter OFDM symbols; the CP adding and CP removing module is used to add and remove cyclic prefix (CP) to eliminate multipath Inter-symbol interference (ISI) caused by the effect; the control module is used to control the workflow and data transmission of the entire system. The specific architecture is omitted.
2.2.1IFFT/FFT module design and implementation
The IFFT/FFT module is one of the core parts of the OFDM system and is used to implement modulation and demodulation of OFDM symbols. IFFT (Inverse Fast Fourier Transform) is used to convert the modulation symbols in the frequency domain to the time domain to form OFDM symbols; FFT (Fast Fourier Transform) is used to convert the received time domain OFDM symbols to the frequency domain for demodulation. The specific algorithm formula and implementation method are omitted.
2.2.2 Design and implementation of shaping filter module
The shaping filter module is used to shape and filter OFDM symbols to reduce out-of-band radiation and improve spectrum utilization. Commonly used shaping filters include raised cosine roll-off filters, root raised cosine roll-off filters, etc. The specific formula and implementation method are omitted.
2.2.3 Design and implementation of adding CP and removing CP module
The CP plus and CP removal module is used to add and remove cyclic prefix (CP) to eliminate inter-symbol interference (ISI) caused by multipath effects. Adding a CP of appropriate length at the transmitting end can ensure that all subcarriers experience the same channel response within a symbol period to avoid ISI; removing the CP at the receiving end can restore the original high-speed data stream. The block diagram of the OFDM system based on IDFT (IFFT) after adding the guard interval is as follows:
3.Verilog core program
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2022/07/27 01:35:32
// Design Name:
// Module Name: TEST_OFDM_tops
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module TEST_OFDM_tops;
reg i_clk;
reg i_rst;
reg i_before_fft1;
reg i_last_fft1;
reg i_enable1;
reg signed[15:0]i_real_dat1;
reg signed[15:0]i_imag_dat1;
wire o_enable_ifft;
wire signed[15:0]o_real_ifft;
wire signed[15:0]o_imag_ifft;
wire o_enable_ifftcp;
wire signed[15:0]o_real_ifftcp;
wire signed[15:0]o_imag_ifftcp;
wire o_enable_fftdcp;
wire signed[15:0]o_real_fftdcp;
wire signed[15:0]o_imag_fftdcp;
wire o_enable_fft;
wire signed[15:0]o_real_fft;
wire signed[15:0]o_imag_fft;
OFDM_tops OFDM_tops_u(
.i_clk (i_clk),
.i_rst (i_rst),
.i_before_fft1 (i_before_fft1),
.i_last_fft1 (i_last_fft1),
.i_enable1 (i_enable1),
.i_real_dat1 (i_real_dat1),
.i_imag_dat1 (i_imag_dat1),
.o_start_ifft (),
.o_ends_ifft (),
.o_enable_ifft (o_enable_ifft),
.o_real_ifft (o_real_ifft),
.o_imag_ifft (o_imag_ifft),
.o_start_ifftcp (),
.o_ends_ifftcp (),
.o_enable_ifftcp (o_enable_ifftcp),
.o_real_ifftcp (o_real_ifftcp),
.o_imag_ifftcp (o_imag_ifftcp),
.o_start_fftdcp (),
.o_ends_fftdcp (),
.o_enable_fftdcp (o_enable_fftdcp),
.o_real_fftdcp (o_real_fftdcp),
.o_imag_fftdcp (o_imag_fftdcp),
.o_start_fft (),
.o_ends_fft (),
.o_enable_fft (o_enable_fft),
.o_real_fft (o_real_fft),
.o_imag_fft (o_imag_fft)
);
reg [15:0]cnts;
always @(posedge i_clk or posedge i_rst)
begin
if(i_rst)
begin
cnts <= 16'd0;
i_real_dat1 <= 16'b1111110000000000;
i_imag_dat1 <= 16'b0000001111111111;
end
else begin
if(i_enable1 == 1'b1)
begin
cnts <= cnts+16'd1;
if(cnts>=16'd200 & cnts<=16'd1848)
begin
i_real_dat1 <= ~i_real_dat1;
if (cnts[0]==1'b1)
i_imag_dat1 <= ~i_imag_dat1;
else
i_imag_dat1 <= i_imag_dat1;
end
end
else begin
cnts <= 16'd0;
i_real_dat1 <= 16'b1111110000000000;
i_imag_dat1 <= 16'b0000001111111111;
end
end
end
reg [19:0]cnts2;
always @(posedge i_clk or posedge i_rst)
begin
if(i_rst)
begin
cnts2 <= 20'd0;
i_before_fft1<=1'b0;
i_enable1 <=1'b0;
i_last_fft1 <=1'b0;
end
else begin
if(cnts2==20'd25000)
cnts2 <= 20'd0;
else
cnts2 <= cnts2 + 20'd1;
if(cnts2==20'd0)
begin
i_before_fft1<=1'b1;
i_enable1 <=1'b0;
i_last_fft1 <=1'b0;
end
if(cnts2==20'd1)
begin
i_before_fft1<=1'b1;
i_enable1 <=1'b0;
i_last_fft1 <=1'b0;
end
if(cnts2==20'd2)
begin
i_before_fft1<=1'b1;
i_enable1 <=1'b0;
i_last_fft1 <=1'b0;
end
if(cnts2==20'd3)
begin
i_before_fft1<=1'b1;
i_enable1 <=1'b0;
i_last_fft1 <=1'b0;
end
if(cnts2==20'd4)
begin
i_before_fft1<=1'b0;
i_enable1 <=1'b0;
i_last_fft1 <=1'b0;
end
if(cnts2>=20'd5 & cnts2<=20'd4+2047)
begin
i_before_fft1<=1'b0;
i_enable1 <=1'b1;
i_last_fft1 <=1'b0;
end
if(cnts2==20'd4+2048)
begin
i_before_fft1<=1'b0;
i_enable1 <=1'b1;
i_last_fft1 <=1'b1;
end
if(cnts2>20'd4+2048)
begin
i_before_fft1<=1'b0;
i_enable1 <=1'b0;
i_last_fft1 <=1'b0;
end
end
end
initial
begin
i_clk = 1'b1;
i_rst = 1'b1;
#2000
i_rst = 1'b0;
end
always #10 i_clk=~i_clk;
endmodule
00_053m4. Obtain the complete algorithm code file
IN