Table of contents
1. Algorithm simulation effect
2. Algorithms involve an overview of theoretical knowledge
4. Complete algorithm code file
1. Algorithm simulation effect
The Vivado2019.2 simulation results are as follows:
After zooming in, you can see:
2. Algorithms involve an overview of theoretical knowledge
Digital AGC (Automatic Gain Control) is an automatic gain control technology widely used in communication systems. It can automatically adjust the gain of the received signal to keep the signal strength within an appropriate range, thereby ensuring the quality of the received signal.
Digital AGC is widely used in communication systems, such as radio communication, satellite communication, radar system and so on. In these applications, digital AGC can ensure that the received signal strength is always within the appropriate range, thus ensuring the quality and reliability of communication. Taking radio communication as an example, digital AGC can enable the receiver to automatically switch between strong and weak signals, thereby avoiding distortion caused by strong signals and noise caused by weak signals. Digital AGC can also reduce energy consumption on the battery and prolong battery life. In satellite communication, digital AGC can make the receiver automatically switch between different antenna directions, and automatically adjust according to the strength of the signal, so as to ensure the quality and reliability of the received signal. In the radar system, digital AGC can ensure that the echo signal strength received by the radar is always within an appropriate range, thereby ensuring the detection distance and detection accuracy of the radar. In a word, digital AGC is a very important technology, which has wide application and development prospects in communication systems, radar systems and other fields.
In this article, we will introduce the principle and working process realization steps of the FPGA-based digital AGC in detail. The basic principle of digital AGC is that after the received signal passes through the front-end amplifier, the signal is processed by sampling, ADC conversion, digital filtering, etc., to obtain the signal strength value, and compare it with the set threshold value, and then compare the front-end signal according to the comparison result. The gain of the amplifier is automatically adjusted to keep the signal strength within an appropriate range. Specifically, the working process of the digital AGC is as follows:
Sampling: After the received signal passes through the front-end amplifier, it is sampled to obtain a series of sampled values.
ADC conversion: convert the sampling value into a digital signal through ADC.
Digital filtering: Digital filtering is performed on the digital signal converted by the ADC to remove high-frequency noise and low-frequency drift.
Square operation: perform square operation on the digitally filtered signal to obtain the power value of the signal.
Moving average: Perform a moving average on the squared signal to obtain the average power value of the signal.
Comparison: compare the average power value with the set threshold to get the comparison result.
Automatic adjustment: According to the comparison result, the gain of the front-end amplifier is automatically adjusted to keep the signal strength within an appropriate range.
The above is the basic principle of digital AGC. Below we describe how to implement a digital AGC in an FPGA.
3. Verilog core program
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//signal 延迟
reg signed[11:0]dly_x[2149:1];
always @(posedge i_clk or posedge i_rst)
begin
if(i_rst)
begin
for(i=1;i<=2149;i=i+1)
dly_x[i]<=12'd0;
end
else begin
dly_x[1]<=i_x;
for(i=2;i<=2149;i=i+1)
dly_x[i]<=dly_x[i-1];
end
end
//flag 延迟
reg signed[2148:0]dly_flag;
always @(posedge i_clk or posedge i_rst)
begin
if(i_rst)
begin
dly_flag<=2149'd0;
end
else begin
dly_flag<={dly_flag[2147:0],i_flag};
end
end
wire signed[11:0]w_y = dly_x[2149];
assign o_flag= dly_flag[2048];
//自动增益
wire [19 : 0] gains;
blk_agc blk_agc_u (
.clka(i_clk), // input wire clka
.rsta(i_rst), // input wire rsta
.addra(o_egy), // input wire [8 : 0] addra
.douta(gains), // output wire [19 : 0] douta
.rsta_busy() // output wire rsta_busy
);
reg signed[19:0]wgains;
always @(posedge i_clk or posedge i_rst)
begin
if(i_rst)
begin
wgains <= 20'b0;
end
else begin
if(o_flag == 1'b1)
wgains <= gains;
else
wgains <= wgains;
end
end
endmodule
00_013m4. Complete algorithm code file
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