1. Algorithm simulation effect

This system has been developed on the Vivado2019.2 platform, and the Vivado2019.2 simulation results are as follows:

Import the 1024 modulated signal into matlab to display the constellation diagram

2. Algorithms involve an overview of theoretical knowledge

This article will introduce the FPGA-based 1024QAM modulation signal generation module in detail. This article will introduce the following aspects: the basic principle of 1024QAM modulation signal, symbol mapping method, parallel processing and FPGA implementation, etc.

2.1. The basic principle of 1024QAM modulation signal

1024QAM modulation is a high-order digital modulation method that maps 10 binary bits to 1024 points on a complex plane. 1024QAM modulated signal can be expressed as:

$$s(t)=A_c \sum_{n=0}^{N-1}a_np(t-nT)cos(2\pi f_ct+\phi_n)$$

Among them, A_c is the carrier amplitude, a_n is 10 binary bits, p(t) is the pulse shaping filter, T is the symbol interval, f_c is the carrier frequency, and \phi_n is the phase.

2.2 Symbol mapping method

There are many options for symbol mapping of the 1024QAM modulated signal, such as Gray mapping, orthogonal mapping, and the like. In this paper, we choose the Gray mapping method, which has better error tolerance and power efficiency.

The idea of Gray mapping is that adjacent symbols have only one bit difference in binary bits. For example, when a_n is 0000000000, the corresponding symbol is the lower left point in the QAM modulation diagram; when a_n is 0000000001, the corresponding symbol is the lower left point moving up by one unit.

2.3 Parallel processing

Since the 1024QAM modulation signal needs to process a large amount of data, it is necessary to adopt a parallel processing method to improve the operation speed and reduce the consumption of hardware resources.

Parallel processing methods include time parallelism and space parallelism. In this paper, we choose the method of time parallelism, which divides the data flow into multiple parallel processing units, and each processing unit is responsible for processing a part of the data to achieve parallel processing. As shown in Figure 3, the 10 binary bits are divided into 5 groups, each group contains two bits, and each bit corresponds to a parallel processing unit.
During parallel processing, data synchronization and data transmission between processing units need to be considered. A common method is to use pipeline processing, that is, the data flow is divided into multiple processing stages, each stage contains multiple parallel processing units, and data transmission and synchronization are performed through registers between adjacent stages.

2.4. FPGA Implementation

FPGA is a flexible and programmable hardware platform that can be customized and implemented according to specific needs. When realizing the FPGA-based 1024QAM modulation signal generation module, it needs to be designed and implemented according to specific hardware resources and computing speed requirements. Usually, the steps of FPGA implementation include hardware description language writing, synthesis, layout and routing, generating bit stream and downloading to FPGA chip, etc. Among them, the writing of the hardware description language is the core of the implementation, which can be written in languages such as Verilog or VHDL.

The realization method of the 1024QAM modulation signal generation module based on FPGA, including the basic principle of 1024QAM modulation signal, symbol mapping method, I parallel processing and FPGA realization, etc. Through reasonable design and optimization, an efficient, stable and reliable 1024QAM modulation signal generation module can be realized, which is suitable for communication, radar, signal processing and other fields.

3. Verilog core program

 
module TEST;

	reg clk;
	reg rst;
	reg start;

    wire  [9:0] parallel_data;
    wire [15:0]sin;
    wire [15:0]cos;
	wire signed[19:0]  I_com;
	wire signed[19:0]  Q_com;
    wire signed[15:0]I_comcos;
    wire signed[15:0]Q_comsin;
	 

	// DUT
	tops_1024QAM_mod  top(
	   .clk(clk),
	   .rst(rst),
	   .start(start),
	   .parallel_data(parallel_data),
	   .sin(sin),
	   .cos(cos),
	   .I_com(I_com),
	   .Q_com(Q_com),
	   .I_comcos(I_comcos),
	   .Q_comsin(Q_comsin)
	   );
	   
	   
//wire signed[23:0]I_comcos2;
//wire signed[23:0]Q_comsin2;
//wire signed[7:0]o_Ifir;
//wire signed[7:0]o_Qfir;
//wire signed[7:0]o_sdout;
//tops_256QAM_demod  top2(
//	   .clk(clk),
//	   .rst(rst),
//	   .start(start),
//	   .I_comcos(I_comcos),
//	   .Q_comsin(Q_comsin),
//	   .I_comcos2(I_comcos2),
//	   .Q_comsin2(Q_comsin2),
//	   .o_Ifir(o_Ifir),
//	   .o_Qfir(o_Qfir),
//	   .o_sdout(o_sdout)
//	   );  
	   
 
	initial begin
		clk = 0;
		rst = 0;
		start = 1;
		#10;
		rst = 1;
	end
	
	always #5
	clk <= ~clk;
	
integer fout1;
integer fout2;
initial begin
 fout1 = $fopen("II.txt","w");
 fout2 = $fopen("QQ.txt","w"); 
end



  reg [4:0]dcnt=5'd0;
  always @(posedge clk) begin
    if(rst == 0) begin
      dcnt <= 0;
 end
      begin
      dcnt <= dcnt+5'd1;
      end 
  end
  
  
always @ (posedge dcnt[4])
 begin
     if(rst==1)
     begin
   	 $fwrite(fout1,"%d\n",I_com);
	 $fwrite(fout2,"%d\n",Q_com);
	 end
end

endmodule
00_024m

4. Complete algorithm code file

m FPGA-based 1024QAM modulation signal generation module verilog implementation, including testbench