m FPGA-based 8ASK modem system verilog implementation, including testbench test files

Table of contents

1. Algorithm simulation effect

2. Summary of theoretical knowledge involved in algorithms

3.Verilog core program

4. Complete algorithm code file

1. Algorithm simulation effect

This system is developed on Vivado2019.2 platform, and the test results are as follows:

The rtl structure is as follows:

2. Summary of theoretical knowledge involved in algorithms

8ASK (Amplitude Octal Keying) is a digital modulation technology that is an extended form of ASK (Amplitude Keying). In 8ASK, the amplitude of the signal is modulated into eight different levels, each level representing three binary bits of information. Therefore, compared with 2ASK and 4ASK, 8ASK can improve data transmission efficiency.

In 8ASK modulation, binary data is first encoded into octal digits, and then the amplitude of the carrier wave is changed to convey this information. Different amplitude levels correspond to different octal numbers, thereby enabling data transmission. During the demodulation process, the original binary data can be restored by detecting the amplitude level of the received signal.

The mathematical expression of 8ASK modulation can be expressed as:

s(t) = A[n] * cos(2πf_ct)

Where, A[n] are eight different amplitude levels, which correspond to the three binary bits of the input; f_c is the frequency of the carrier. This formula describes how binary data is mapped to different amplitude levels and modulated by cosine waves.

During the demodulation process, the envelope detection method is usually used to restore the original signal. The envelope detector extracts the amplitude envelope of the received signal and compares it with a preset amplitude level to determine the corresponding binary data.

3. FPGA implementation process

Modulator design: First, design the 8ASK modulator on FPGA. The modulator receives three bits of binary data as input and selects the appropriate amplitude level based on the input data. Then, digital signal processing technology is used to generate a cosine wave of corresponding amplitude and output as a modulated signal.
Demodulator design: Next, design the 8ASK demodulator. The demodulator receives the modulated signal transmitted through the channel and first performs preprocessing operations such as signal amplification and filtering. Then, the amplitude envelope of the received signal is extracted through the envelope detection method. Compare the amplitude envelope with the preset amplitude level, determine the closest level, and convert it into the corresponding three-digit binary data as the output.
Digital signal processing: During FPGA implementation, digital signal processing technology needs to be used to generate modulated signals and process received signals. This includes the use of look-up tables (LUTs) to store precomputed cosine wave amplitude values, and the use of digital filters for operations such as signal filtering and shaping.
Performance testing and optimization: After completing the design of the modulator and demodulator, performance testing and optimization are required. By simulating input of different binary data, observe the correctness and bit error rate of the demodulation output and other indicators. Based on the test results, the design can be adjusted and optimized, such as changing the interval of the amplitude levels, adjusting the parameters of the filter, etc., to improve the performance of the system.

3.Verilog core program

`timescale 1ns / 1ps
//
 
//
 

module test_8ASK;
 
reg i_clk;
reg i_rst;
reg[2:0]i_bits;
wire signed[15:0]o_8ask;
wire signed[31:0]o_de_8askf;
wire [2:0]o_bits;


 

ASK8 uut(
.i_clk(i_clk),
.i_rst(i_rst),
.i_bits(i_bits),
.o_8ask(o_8ask),
.o_de_8ask(),
.o_de_8askf(o_de_8askf),
.o_bits(o_bits)
);

initial
begin
    i_clk = 1'b1;
    i_rst = 1'b1;
    #1000
    i_rst = 1'b0;
end
initial
begin
    i_bits= 3'b000;
    #1024
    i_bits= 3'b001;
    #256
    i_bits= 3'b010;
    #512
    i_bits= 3'b011;
    #512
    i_bits= 3'b100;
    #512
    i_bits= 3'b101;
    #1024
    i_bits= 3'b110;
    #512
    i_bits= 3'b111;
    #256
    i_bits= 3'b111;
    #128
    i_bits= 3'b100;
    #128
    i_bits= 3'b001;
    repeat(100)
    begin
    #256
    i_bits= 3'b000;
    #2048
    i_bits= 3'b001;
    #2048
    i_bits= 3'b010;
    #2048
    i_bits= 3'b011;
    #2048
    i_bits= 3'b100;
    #2048
    i_bits= 3'b101;
    #1024
    i_bits= 3'b110;
    #1024
    i_bits= 3'b111;
    #1024
    i_bits= 3'b010;
    #512
    i_bits= 3'b001;
    #512
    i_bits= 3'b011;
    #512
    i_bits= 3'b111;
    #256
    i_bits= 3'b101;
    #256
    i_bits= 3'b111;
    #512
    i_bits= 3'b100;
    #256
    i_bits= 3'b001;
    #128
    i_bits= 3'b001;
    
    #128
    i_bits= 3'b001;
    #128
    i_bits= 3'b110;
    #1024
    i_bits= 3'b010;
    #512
    i_bits= 3'b111;
    #128
    i_bits= 3'b001;
    #256
    i_bits= 3'b100;
    #128
    i_bits= 3'b110;
    #256
    i_bits= 3'b010;
    end
end



always #1 i_clk=~i_clk;

endmodule
00_051m