m FPGA-based 4ASK modem system verilog implementation, including testbench test files

Table of contents

1. Algorithm simulation effect

2. Summary of theoretical knowledge involved in algorithms

3.Verilog core program

4. Complete algorithm code file

1. Algorithm simulation effect

This system is developed on Vivado2019.2 platform, and the test results are as follows:

The rtl structure is as follows:

2. Summary of theoretical knowledge involved in algorithms

With the continuous development of communication technology, multi-ary digital modulation methods have gradually attracted people's attention. Among them, 4ASK (quaternary amplitude keying), as an effective modulation method, has broad application prospects in communication systems. 4ASK modulation is a multi-digit digital modulation method that uses four different amplitude levels to represent four different symbols, each symbol corresponding to two bits of binary information. In 4ASK modulation, information is transmitted by changing the amplitude of the carrier wave, and different amplitude levels correspond to different binary code words. During the demodulation process, the receiver determines the original binary information based on the received signal amplitude. Compared with 2ASK, 4ASK modulation has higher band utilization because it can convey more information in each symbol period. However, as the base number increases, the complexity of modulation and demodulation also increases accordingly, and the requirements for the channel become more stringent.

The mathematical expression of 4ASK modulation can be expressed as:

s(t) = A[m] * cos(2πfct + φ)

Among them, A[m] represents four different amplitude levels, which correspond to the input two-digit binary codeword; fc represents the frequency of the carrier; φ represents the initial phase of the carrier. In the demodulation process, envelope detection or coherent demodulation methods are usually used to restore the original binary information.

Implementing the 4ASK modulation and demodulation system on FPGA is mainly divided into the following steps:

System design: Design the overall architecture of the system based on the principle of 4ASK modulation and demodulation. Including input interface, modulator, demodulator, output interface and other parts. Determine the connection relationships and data flows between various modules.
Verilog coding: Use Verilog language to code each module. For the modulator module, the corresponding amplitude level is selected based on the input two-bit binary code word and a modulated signal is generated. The demodulator module receives the modulated signal and restores the original binary information through envelope detection or coherent demodulation. At the same time, it is also necessary to design appropriate auxiliary modules such as filters and clock modules to achieve complete modulation and demodulation functions.
Simulation verification: After completing the coding, verify the designed system through simulation tools. You can use test vectors or simulated signals as input to observe whether the modulation and demodulation output behaves as expected. By continuously adjusting and optimizing parameters, we ensure that the performance and stability of the system meet the requirements.

3.Verilog core program

`timescale 1ns / 1ps
//
 
module test_ASK4;
 
reg i_clk;
reg i_rst;
reg[1:0]i_bits;
wire signed[15:0]o_4ask;
wire signed[31:0]o_de_4askf;
wire [1:0]o_bits;


 

ASK4 uut(
.i_clk(i_clk),
.i_rst(i_rst),
.i_bits(i_bits),
.o_4ask(o_4ask),
.o_de_4ask(),
.o_de_4askf(o_de_4askf),
.o_bits(o_bits)
);

initial
begin
    i_clk = 1'b1;
    i_rst = 1'b1;
    #1000
    i_rst = 1'b0;
end
initial
begin
    i_bits= 2'b00;
    #1024
    i_bits= 2'b1;
    #256
    i_bits= 2'b0;
    #512
    i_bits= 2'b1;
    #512
    i_bits= 2'b1;
    #512
    i_bits= 2'b1;
    #1024
    i_bits= 2'b0;
    #512
    i_bits= 2'b0;
    #256
    i_bits= 2'b1;
    #128
    i_bits= 2'b1;
    #128
    i_bits= 2'b0;
    repeat(100)
    begin
    #256
    i_bits= 2'b0;
    #2048
    i_bits= 2'b11;
    #2048
    i_bits= 2'b00;
    #2048
    i_bits= 2'b01;
    #2048
    i_bits= 2'b10;
    #2048
    i_bits= 2'b00;
    #1024
    i_bits= 2'b11;
    #1024
    i_bits= 2'b10;
    #1024
    i_bits= 2'b10;
    #512
    i_bits= 2'b01;
    #512
    i_bits= 2'b10;
    #512
    i_bits= 2'b10;
    #256
    i_bits= 2'b10;
    #256
    i_bits= 2'b00;
    #512
    i_bits= 2'b01;
    #256
    i_bits= 2'b10;
    #128
    i_bits= 2'b00;
    
    #128
    i_bits= 2'b10;
    #128
    i_bits= 2'b11;
    #1024
    i_bits= 2'b01;
    #512
    i_bits= 2'b00;
    #128
    i_bits= 2'b11;
    #256
    i_bits= 2'b10;
    #128
    i_bits= 2'b10;
    #256
    i_bits= 2'b00;
    end
end



always #1 i_clk=~i_clk;

endmodule
00_050m