m FPGA-based 16QAM soft demodulation verilog implementation, including testbench

Table of contents

1. Algorithm simulation effect

2. Algorithms involve an overview of theoretical knowledge

3. Verilog core program

4. Complete algorithm code file


1. Algorithm simulation effect


The system has been developed on two platforms, namely:

Vivado2019.2

Quartusii18.0+ModelSim-Altera 6.6d Starter Edition

The Vivado2019.2 simulation results are as follows:

 

 The test results of Quartusii18.0+ModelSim-Altera 6.6d Starter Edition are as follows:

 

2. Algorithms involve an overview of theoretical knowledge

        16QAM soft demodulation is a commonly used digital modulation and demodulation technology, which is used to convert the received 16QAM modulated signal into original data. This technology combines 16 phase and amplitude modulation methods, and demodulates the received signal through a soft decision algorithm. The system principle of 16QAM soft demodulation is to convert the received 16QAM modulated signal into a soft decision result, thereby restoring the original data. Soft demodulation is a non-hard decision demodulation method, which uses the sampling value and phase information of the received signal to judge the modulation state of the signal and demodulate it. In 16QAM soft demodulation, after the received signal is sampled, the nearest modulation point is selected as the demodulation result by comparing the distance between the sampled value and 16 modulation points.

       16QAM modulation maps every four bits to a complex point, and there are 16 modulation modes of phase and amplitude. Each complex point corresponds to a modulation symbol. Through soft demodulation, we can determine the modulation symbol corresponding to the received signal, and then derive the original data.

       Assuming that the sampling value of the received signal is $r$, we need to select the nearest modulation point by comparing the distance between $r$ and 16 modulation points.

Demodulation process
The following are the specific steps of 16QAM soft demodulation:

Step 1: Receive Signal Sampling

The received signal undergoes a sampling process to obtain the sampled value $r$.

Step 2: Calculate the distance

Calculate the distance $d_i$ between the sampling value $r$ and each modulation point, where $i=1,2,...,16$. Distances can be calculated using Euclidean distance or other metrics.

Step 3: Select the nearest modulation point

Select the modulation point closest to the sampling value $r$, record it as $d_{\min}$, and record its index $i_{\min}$.

Step 4: Soft Judgment

According to the index $i_{\min}$, determine the modulation symbol corresponding to the received signal. According to the modulation symbol, the original data can be derived.

Mathematical formula example
The following is a mathematical formula example for 16QAM soft demodulation:

For the sample value $r$ of the received signal, the distance $d_i$ from each modulation point can be calculated as:

Select the nearest modulation point and corresponding index: 

According to the index $i_{\min}$, the modulation symbol corresponding to the received signal can be determined, and the original data can be further derived.

     The difficulty in realizing 16QAM soft demodulation lies in choosing an appropriate distance measurement method and decision threshold, and making accurate decisions in the presence of noise. In addition, the mapping problem of modulation points needs to be solved to ensure that soft demodulation can accurately restore the original data.

       In summary, 16QAM soft demodulation is a method to demodulate the received signal by comparing the distance between the sampling value and the modulation point and selecting the nearest modulation point. Through soft demodulation, the original data can be restored and efficient data transmission can be achieved.

3. Verilog core program

`timescale 1ns / 1ns
module TEST;

	reg clk;
 
	reg rst;
	reg start;

    wire  [3:0] parallel_data;
    wire [15:0]sin;
    wire [15:0]cos;
	wire signed[19:0]  I_com;
	wire signed[19:0]  Q_com;
    wire signed[15:0]I_comcos;
    wire signed[15:0]Q_comsin;
	 

	// DUT
	tops_16QAM_mod  top(
	   .clk(clk),
	   .rst(rst),
	   .start(start),
	   .parallel_data(parallel_data),
	   .sin(sin),
	   .cos(cos),
	   .I_com(I_com),
	   .Q_com(Q_com),
	   .I_comcos(I_comcos),
	   .Q_comsin(Q_comsin)
	   );
	   
	   
wire signed[23:0]I_comcos2;
wire signed[23:0]Q_comsin2;
wire signed[7:0]o_Ifir;
wire signed[7:0]o_Qfir;
wire signed[15:0]o_b1;
wire signed[15:0]o_b2;
wire signed[15:0]o_b3;
wire signed[15:0]o_b4;
wire signed[3:0]o_sdout;
tops_16QAM_demod  top2(
	   .clk(clk),
 
	   .rst(rst),
	   .start(start),
	   .I_comcos(I_comcos),
	   .Q_comsin(Q_comsin),
	   .I_comcos2(I_comcos2),
	   .Q_comsin2(Q_comsin2),
	   .o_Ifir(o_Ifir),
	   .o_Qfir(o_Qfir),
	   .o_b1(o_b1),
	   .o_b2(o_b2),
	   .o_b3(o_b3),
	   .o_b4(o_b4),
	   .o_sdout(o_sdout)
	   );  
	   
 
	initial begin
		clk = 0;
		rst = 0;
		start = 1;
		#10;
		rst = 1;
	end
	
	always #5
	clk <= ~clk;
	
integer fout1;
integer fout2;
initial begin
 fout1 = $fopen("II.txt","w");
 fout2 = $fopen("QQ.txt","w"); 
end

always @ (posedge clk)
 begin
     if(rst==1)
     begin
   	 $fwrite(fout1,"%d\n",I_com);
	 $fwrite(fout2,"%d\n",Q_com);
	 end
end

endmodule
00_027m

4. Complete algorithm code file

V

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Origin blog.csdn.net/hlayumi1234567/article/details/131795255