1. Algorithm simulation effect

The system has been developed on two platforms, namely:

Vivado2019.2

Quartusii18.0+ModelSim-Altera 6.6d Starter Edition

The Vivado2019.2 simulation results are as follows:

Perform 2-way, 4-way, 8-way, 16-way parallel-serial conversion respectively

The test results of Quartusii18.0+ModelSim-Altera 6.6d Starter Edition are as follows:

2. Algorithms involve an overview of theoretical knowledge

Serial-to-parallel conversion is the process of converting serial data into parallel data, that is, splitting a string of data into multiple parallel data bits. The input to the serial-to-parallel converter is a serial data stream and the output is a parallel data stream. In a serial-to-parallel converter, a shift register is used to store the serial data and a multiplexer is used to select the data bits to output on the parallel bus.
Parallel-to-serial conversion is the process of converting parallel data into serial data, that is, combining multiple parallel data into a series of data. Parallel converters have a parallel data stream as their input and a serial data stream as their output. In a parallel to serial converter, a multiplexer is used to select the data bits, and a shift register is used to store the parallel data, which is combined bit by bit into serial data.

2.1 FPGA realization of serial-to-parallel conversion

The FPGA realization of serial-to-parallel converter needs to use shift registers and multiplexers to realize. The specific steps are as follows:
Design the shift register: design the size of the shift register according to the number of input data bits and the number of output data bits, and store the input data stream into the shift register.
Design a multiplexer: According to the number of output data bits and the size of the shift register, design the size of the multiplexer, and use the multiplexer to select data bits and output them to the parallel bus.
Design sequential logic: design clock control circuit and shift control circuit to control data shift and selection.
Design output interface: design parallel output bus and output interface to output parallel data to external devices.

2.2 FPGA Realization of Parallel-to-Serial Conversion

The FPGA realization of the parallel-to-serial converter needs to use shift registers and multiplexers to realize. The specific steps are as follows:
Design the shift register: design the size of the shift register according to the number of input data bits and output data bits, and store the input data into the shift register.
Design a multiplexer: According to the number of input data bits and output data bits, design the size of the multiplexer, and use the multiplexer to select data bits and combine them into serial data.
Design sequential logic: design clock control circuit and shift control circuit to control data shift and selection.
Design the input interface: design the parallel input bus and input interface, and input the parallel data into the shift register.

3. Verilog core program

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2023/05/07 19:40:52
// Design Name: 
// Module Name: TEST
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module TEST();

reg i_clk;
reg i_rst;
reg i_din;  
wire[15:0]o_datp;  
wire     o_dats;  
s2p s2pu1(  
             .i_clk  (i_clk),
             .i_rst  (i_rst),
             .i_sel  (2'b00),//00锛?路01:4路10鈥?路11锛?6路
             .i_din  (i_din),
 
             .o_datp (o_datp)          
             );
    
p2s p2su2(
             .i_clk  (i_clk),
             .i_rst  (i_rst),
             .i_sel  (2'b00),//00锛?路01:4路10鈥?路11锛?6路
             .i_din  (o_datp),
             .o_dats (o_dats)         
             );
             
             
initial
begin
i_clk=1'b1;
i_rst=1'b1;
#1000
i_rst=1'b0;
end

always #5 i_clk=~i_clk;

initial
begin
i_din=1'b0;
#1000
i_din=1'b1;
#10
i_din=1'b1;
#10
i_din=1'b0;
#10
i_din=1'b1;
#10
i_din=1'b1;
#10
i_din=1'b0;
#10
i_din=1'b1;
#10
i_din=1'b1;
#10
i_din=1'b0;
#10
i_din=1'b1;
#10
i_din=1'b1;
#10
i_din=1'b0;
#10
i_din=1'b1;
#10
i_din=1'b1;
#10
i_din=1'b0;
#10
i_din=1'b1;




#10
i_din=1'b1;
#10
i_din=1'b0;
#10
i_din=1'b0;
#10
i_din=1'b1;
#10
i_din=1'b0;
#10
i_din=1'b0;
#10
i_din=1'b1;
#10
i_din=1'b0;
#10
i_din=1'b1;
#10
i_din=1'b0;
#10
i_din=1'b0;
#10
i_din=1'b1;
#10
i_din=1'b1;
#10
i_din=1'b1;
#10
i_din=1'b1;
#10
i_din=1'b0;

#500
$stop();


end

endmodule
00_010m

4. Complete algorithm code file

m FPGA-based data serial-to-parallel conversion system verilog implementation, including testbench, can configure the number of parallel

1. Algorithm simulation effect

2. Algorithms involve an overview of theoretical knowledge

3. Verilog core program

4. Complete algorithm code file

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