m FPGA-based basic OFDM modulation and demodulation verilog implementation, including IFFT and FFT, including testbench

Table of contents

1. Algorithm simulation effect

2. Algorithms involve an overview of theoretical knowledge

3. Verilog core program

4. Complete algorithm code file


1. Algorithm simulation effect

The Vivado2019.2 simulation results are as follows:

2. Algorithms involve an overview of theoretical knowledge

       Orthogonal Frequency Division Multiplexing (OFDM) is a multi-carrier modulation technology. Its basic principle is to divide a high-speed data signal into multiple low-speed sub-carriers, modulate data on each sub-carrier, and superimpose all sub-carriers Together they form an OFDM signal. OFDM signal has a good ability to resist multipath fading and frequency selective fading, so it is widely used in wireless communication and digital TV and other fields.

      The main idea of ​​OFDM is: divide the channel into several orthogonal sub-channels, convert high-speed data signals into parallel low-speed sub-data streams, and modulate them for transmission on each sub-channel. Orthogonal signals can be separated by using correlation techniques at the receiver, which can reduce the mutual interference (ISI) between subchannels. The signal bandwidth on each sub-channel is smaller than the relevant bandwidth of the channel, so each sub-channel can be regarded as flat fading, which can eliminate intersymbol interference, and because the bandwidth of each sub-channel is only a small part of the original channel bandwidth, the channel Equilibrium becomes relatively easy.

        OFDM technology is the basis of the HPA Alliance (HomePlug Powerline Alliance) industrial specification. It uses a discontinuous multi-tone technology to combine a large number of signals in different frequencies called carriers into a single signal to complete signal transmission. Because this technology has the ability to transmit signals under clutter interference, it is often used in transmission media that are susceptible to external interference or have poor ability to resist external interference.

       An OFDM symbol contains multiple subcarriers that have undergone phase shift keying (PSK) or quadrature amplitude modulation (QAM).

       Once the transmitted bits are allocated to each subcarrier, a certain modulation mode maps them to the amplitude and phase of the subcarrier, and the equivalent baseband signal is usually used to describe the OFDM output signal:

The real part and imaginary part of the signal correspond to the in-phase and quadrature components of OFDM respectively, and can be multiplied by the corresponding cos coscos component and sin sinsin component in the actual system.


       The OFDM modulation and demodulation system consists of a transmitter and a receiver. At the transmitting end, the input digital signal is modulated and processed by IFFT to form an OFDM signal, sent to the radio frequency module for radio frequency processing, and finally sent through the antenna. At the receiving end, the received OFDM signal is processed by the radio frequency front-end, and the digital signal is output after FFT transformation and demodulation.

   The design process of the OFDM modulation and demodulation system can be divided into the following steps:

      System requirements analysis: According to the application scenarios and performance requirements of the system, determine the functional modules, data processing methods, interface specifications and performance indicators of the system, etc.
      System architecture design: design the hardware platform, software platform, communication interface and data transmission mode of the system, and determine the overall architecture and module division of the system.
       Functional module design: Design each functional module of the system, including OFDM modulation module, IFFT module, FFT module, demodulation module, etc.


3. Verilog core program

`timescale 1ns / 1ps
 

module OFDM_tops(
                i_clk,
                i_rst,
                
                i_before_fft1,
                i_last_fft1,
                i_enable1,
                i_real_dat1,
                i_imag_dat1,


                o_start_ifft,
                o_ends_ifft,
                o_enable_ifft, 
                o_real_ifft,
                o_imag_ifft,
                
                
                o_start_fft,
                o_ends_fft,
                o_enable_fft, 
                o_real_fft,
                o_imag_fft 
                );
    
input             i_clk;                 
input             i_rst;   
      
input             i_before_fft1;                
input             i_last_fft1;   
input             i_enable1;  
input signed[15:0]i_real_dat1;                 
input signed[15:0]i_imag_dat1;   


output  o_start_ifft;
output  o_ends_ifft;
output  o_enable_ifft;
output signed[31:0]o_real_ifft;                 
output signed[31:0]o_imag_ifft;


output  o_start_fft;
output  o_ends_fft;
output  o_enable_fft;
output signed[31:0]o_real_fft;                 
output signed[31:0]o_imag_fft;  






Tants Tantsu1(
                .i_clk          (i_clk),
                .i_rst          (i_rst),
                
                .i_before_fft1  (i_before_fft1),
                .i_last_fft1    (i_last_fft1),
                .i_enable1      (i_enable1),
                .i_real_dat     (i_real_dat1),
                .i_imag_dat     (i_imag_dat1),
 
                .o_real_ifft    (o_real_ifft),
                .o_imag_ifft    (o_imag_ifft),
                .o_start        (o_start_ifft),
                .o_ends         (o_ends_ifft),
                .o_enable       (o_enable_ifft)
                 
                );
 
 
 
Rants Rantsu1(
                .i_clk          (i_clk),
                .i_rst          (i_rst),
 
                .i_before_fft1  (o_start_ifft),
                .i_last_fft1    (o_ends_ifft),
                .i_enable1      (o_enable_ifft),
                .i_real_dat     (o_real_ifft[31-5:7]),
                .i_imag_dat     (o_imag_ifft[31-5:7]),
                
                .o_real_fft     (o_real_fft),
                .o_imag_fft     (o_imag_fft),
                .o_start        (o_start_fft),
                .o_ends         (o_ends_fft),
                .o_enable       (o_enable_fft)
                );
 
endmodule
00_009m


4. Complete algorithm code file

V
 

Guess you like

Origin blog.csdn.net/hlayumi1234567/article/details/130548868