Table of contents
1. Algorithm simulation effect
2. Algorithms involve an overview of theoretical knowledge
4. Complete algorithm code file
1. Algorithm simulation effect
The system has been developed on two platforms, namely:
Vivado2019.2
Quartusii18.0+ModelSim-Altera 6.6d Starter Edition
The Vivado2019.2 simulation results are as follows:
The test results of Quartusii18.0+ModelSim-Altera 6.6d Starter Edition are as follows:
matlab test:
2. Algorithms involve an overview of theoretical knowledge
QPSK is a commonly used modulation method, which realizes efficient signal transmission by mapping two bits to a phase point on a complex plane. Soft demodulation is a method of demodulation based on the probability estimate of the received signal, which can provide better performance. This article will gradually introduce the implementation process of QPSK soft demodulation, including signal sampling, phase estimation, decision and demodulation. Soft demodulation is a method to achieve demodulation by probabilistic estimation, which can provide better performance in the presence of channel noise. QPSK is a commonly used modulation method that enables efficient signal transmission by mapping two bits to phase points. This article aims to introduce the implementation process of QPSK soft demodulation in detail, including steps such as signal sampling, phase estimation, decision and demodulation.
Realize step
2.1 signal sampling
The received QPSK signal undergoes a sampling operation to obtain a discrete time signal sequence. The sampling rate needs to satisfy the Nyquist sampling theorem and is usually twice the bit rate.
2.2 Judgment
In QPSK signal demodulation, the decision process is used to determine the binary bit value of each signal symbol. The decision process divides according to the phase of the received signal, mapping it to different bit values.
Assuming that the received signal sequence is r[n], the result of the decision process is the decision symbol d_hat. A common judgment formula is:
if theta_hat > -pi/4 && theta_hat <= pi/4
d_hat = [1, 1]
elseif theta_hat > pi/4 && theta_hat <= 3pi/4
d_hat = [0, 1]
elseif theta_hat > 3pi/4 || theta_hat <= -3*pi/4
d_hat = [0, 0]
else
d_hat = [1, 0]
end
2.3 demodulation
The demodulation process converts the decided bit values into raw data bits. The demodulation process converts the decision bit value into the original data bit according to the mapping table. Assuming that the decision bit value is d_hat, the result of the demodulation process is demodulation bit d. The common demodulation formula is:
if d_hat == [1, 1]
d = [0, 0]
elseif d_hat == [0, 1]
d = [0, 1]
elseif d_hat == [0, 0]
d = [1, 0]
else
d = [1, 1]
end
2.4 Soft demodulation
Soft demodulation is the key step of QPSK soft demodulation, it uses the result of decision symbol and phase estimation to carry out probability estimation, in order to improve the accuracy of demodulation. Assuming that the decision symbol is d_hat, the result of the soft demodulation process is the soft demodulation symbol d. The common soft demodulation formula is: d = d_hat / P(d_hat|r[n])
Among them, P(d_hat|r[n]) represents the probability that the decision symbol d_hat is d_hat under the condition that the signal r[n] is received. The probability can be obtained by estimating the probability distribution function of signal points or using methods such as maximum likelihood estimation. The soft demodulation process needs probability estimation to improve the accuracy of demodulation. This involves estimating the probability distribution function of the signal points or using other probability estimation methods, where the effect of noise needs to be properly accounted for.
3. Verilog core program
`timescale 1ns / 1ps
module TEST();
reg i_clk;
reg i_clkSYM;
reg i_rst;
reg i_dat;
wire signed[15:0]o_Ifir_T;
wire signed[15:0]o_Qfir_T;
wire signed[15:0]o_cos_T;
wire signed[15:0]o_sin_T;
wire signed[31:0]o_modc_T;
wire signed[31:0]o_mods_T;
wire signed[31:0]o_mod_T;
wire signed[15:0]o_cos_R;
wire signed[15:0]o_sin_R;
wire signed[31:0]o_modc_R;
wire signed[31:0]o_mods_R;
wire signed[31:0]o_Ifir_R;
wire signed[31:0]o_Qfir_R;
wire signed[15:0]o_b1;
wire signed[15:0]o_b2;
wire signed[15:0]o_dat;
//QPSK调制
TQPSK TQPSKU(
.i_clk (i_clk),
.i_clkSYM(i_clkSYM),
.i_rst (i_rst),
.i_dat(i_dat),
.o_Ifir (o_Ifir_T),
.o_Qfir (o_Qfir_T),
.o_cos (o_cos_T),
.o_sin (o_sin_T),
.o_modc (o_modc_T),
.o_mods (o_mods_T),
.o_mod (o_mod_T)
);
//QPSK解调
RQPSK RQPSKU(
.i_clk (i_clk),
.i_rst (i_rst),
.i_clkSYM(i_clkSYM),
.i_med (o_mod_T[25:10]),
.o_cos (o_cos_R),
.o_sin (o_sin_R),
.o_modc (o_modc_R),
.o_mods (o_mods_R),
.o_Ifir (o_Ifir_R),
.o_Qfir (o_Qfir_R),
.o_b1 (o_b1),
.o_b2 (o_b2),
.o_dat (o_dat)
);
initial
begin
i_clk = 1'b1;
i_clkSYM=1'b1;
i_rst = 1'b1;
#1600
i_rst = 1'b0;
end
always #5 i_clk=~i_clk;
always #80 i_clkSYM=~i_clkSYM;
initial
begin
i_dat = 1'b0;
#1440
repeat(10)
begin
#160 i_dat = 1'b1;
#160 i_dat = 1'b1;
#160 i_dat = 1'b0;
#160 i_dat = 1'b0;
#160 i_dat = 1'b0;
#160 i_dat = 1'b1;
#160 i_dat = 1'b0;
#160 i_dat = 1'b1;
#160 i_dat = 1'b1;
#160 i_dat = 1'b0;
#160 i_dat = 1'b0;
#160 i_dat = 1'b0;
#160 i_dat = 1'b0;
#160 i_dat = 1'b0;
#160 i_dat = 1'b0;
#160 i_dat = 1'b0;
#160 i_dat = 1'b0;
#160 i_dat = 1'b0;
#160 i_dat = 1'b1;
#160 i_dat = 1'b1;
#160 i_dat = 1'b1;
#160 i_dat = 1'b0;
#160 i_dat = 1'b0;
#160 i_dat = 1'b1;
#160 i_dat = 1'b0;
#160 i_dat = 1'b0;
#160 i_dat = 1'b1;
#160 i_dat = 1'b1;
#160 i_dat = 1'b0;
end
$stop();
end
//reg[7:0]cmnts;
//always @(posedge i_clk or posedge i_rst)
//begin
// if(i_rst)
// begin
// cmnts <= 8'd0;
// i_Ibits_T<=1'b0;
// i_Qbits_T<=1'b0;
// end
//else begin
// cmnts <= cmnts + 8'd1;
// i_Ibits_T<=cmnts[5];
// i_Qbits_T<=cmnts[6];
// end
//end
endmodule
00_026m4. Complete algorithm code file
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