Table of contents
1. Algorithm simulation effect
2. Algorithms involve an overview of theoretical knowledge
4. Complete algorithm code file
1. Algorithm simulation effect
The system has been developed on two platforms, namely:
Vivado2019.2
Quartusii18.0+ModelSim-Altera 6.6d Starter Edition
The Vivado2019.2 simulation results are as follows:
The test results of Quartusii18.0+ModelSim-Altera 6.6d Starter Edition are as follows:
2. Algorithms involve an overview of theoretical knowledge
In modern communication systems, in order to ensure the reliability and security of data transmission, certain encryption and decryption techniques are usually required. Data scrambling and descrambling are one of the important means, they can effectively resist various interference and attacks without increasing the transmission overhead. This article will introduce the principles, advantages and FPGA implementation process of data scrambling and descrambling in detail.
1. The principle of data scrambling
Data scrambling refers to the transformation of the original data before data transmission, so that the data presents more random characteristics during transmission. This can effectively resist various forms of interference, including electromagnetic interference, channel noise, multipath fading, etc. The basic principle of data scrambling is to transform the original data through a certain algorithm, so that the transformed data is different from the original data in statistical characteristics. In this way, the influence of interference and noise in the transmission process on the data can be reduced, thereby improving the reliability of data transmission.
There are many ways to implement data scrambling, and the more common ways include XOR scrambling, permutation scrambling, and chaos scrambling. XOR scrambling is the simplest scrambling method. Its principle is to perform XOR operation on original data and a random number sequence to obtain scrambled data. Permutation scrambling refers to performing a certain permutation operation on the original data to make the scrambled data more random. Chaos scrambling is to use the characteristics of chaotic system to scramble, generate random sequence through chaotic map or chaotic flow, and then perform XOR operation on original data and random sequence to obtain scrambled data.
2. Principle of data descrambling
Data descrambling refers to decrypting the scrambled data to restore the original data. The principle of data descrambling is similar to that of data scrambling, and the opposite operation method is usually used to restore the scrambled data to the original data. If the XOR scrambling method is adopted, the descrambling method is to perform an XOR operation on the scrambled data and the random number sequence again. If the permutation scrambling method is adopted, the descrambling method is to perform the corresponding permutation operation on the scrambled data again. If the chaotic scrambling method is adopted, the descrambling method is to perform an XOR operation on the random sequence generated by the chaotic system and the scrambled data, so as to restore the original data.
3. Advantages of data scrambling and descrambling
Data scrambling and descrambling technology has the following advantages:
(1) Improving transmission reliability: The scrambled data has more random characteristics, which can effectively resist various forms of interference and attacks, thereby improving the reliability of data transmission .
(2) No increase in transmission overhead: The algorithms for data scrambling and descrambling can be implemented during transmission, without additional transmission overhead and without increasing transmission delay.
(3) Protect data security: The scrambled data has higher security, which can effectively prevent data leakage and illegal access, and protect data security.
4. FPGA implementation process
FPGA is a programmable logic device, which can be programmed to realize various functions according to application requirements. In data scrambling and descrambling, FPGA can implement scrambling and descrambling algorithms and apply them in communication systems to improve the reliability and security of data transmission.
The process of FPGA implementing data scrambling can be divided into the following steps:
(1) Design scrambling algorithm: According to the application requirements, design a suitable scrambling algorithm, including XOR scrambling, permutation scrambling and chaotic scrambling. When designing a scrambling algorithm, it is necessary to consider whether the scrambled data is sufficiently random and secure.
(2) Realize the scrambling algorithm: convert the scrambling algorithm into an FPGA programmable language, such as VHDL or Verilog. When implementing the scrambling algorithm, the efficiency and complexity of the algorithm need to be considered to ensure that it can be implemented on the FPGA.
(3) Design FPGA circuit: According to the scrambling algorithm, design FPGA circuit, including input and output ports, scrambling logic circuit, clock circuit, etc. When designing an FPGA circuit, it is necessary to consider the power consumption and area of the circuit to ensure that the circuit can be implemented on the FPGA.
(4) Compile and download: Compile the designed FPGA circuit into a bitstream file and download it to the FPGA chip. When downloading, you need to pay attention to parameters such as the model and clock frequency of the FPGA chip to ensure that the circuit can work normally.
The process of FPGA realizing data descrambling is similar to data scrambling, mainly including steps such as designing descrambling algorithm, implementing descrambling algorithm, designing FPGA circuit, compiling and downloading. It should be noted that when implementing the descrambling algorithm, it is necessary to consider the corresponding relationship between the descrambling algorithm and the scrambling algorithm, so as to ensure that the original data can be restored correctly.
Data scrambling and descrambling are commonly used data protection techniques in modern communication systems, which can improve the reliability and security of data transmission. In practical applications, FPGA can implement scrambling and descrambling algorithms and apply them in communication systems. The process of FPGA implementing data scrambling and descrambling includes the steps of designing algorithm, implementing algorithm, designing FPGA circuit, compiling and downloading, etc. It is necessary to consider the efficiency and complexity of the algorithm, as well as the power consumption and area of the circuit.
3. Verilog core program
`timescale 1ns / 1ps
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module TEST();
reg i_clk;
reg i_rst;
reg i_enable;
reg i_start;
reg i_din;
wire o_enable_scr;
wire o_start_scr;
wire o_dout_scr;
wire o_enable_dscr;
wire o_start_dscr;
wire o_dout_dscr;
tops uut(
.i_clk (i_clk),
.i_rst (i_rst),
.i_enable (i_enable),
.i_start (i_start),
.i_din (i_din),
.o_enable_scr (o_enable_scr),
.o_start_scr (o_start_scr),
.o_dout_scr (o_dout_scr),
.o_enable_dscr (o_enable_dscr),
.o_start_dscr (o_start_dscr),
.o_dout_dscr (o_dout_dscr)
);
initial
begin
i_clk = 1'b1;
i_rst = 1'b1;
#1000
i_rst = 1'b0;
end
initial
begin
i_enable = 1'b0;
#1000
i_enable = 1'b1;
#1280
i_enable = 1'b0;
end
initial
begin
i_start = 1'b0;
#1000
i_start = 1'b1;
#10
i_start = 1'b0;
end
initial
begin
i_din = 1'b0;
#1000
i_din = 1'b0;
#10
i_din = 1'b1;
#100
i_din = 1'b0;
#50
i_din = 1'b1;
#140
i_din = 1'b0;
#120
i_din = 1'b1;
#30
i_din = 1'b0;
#20
i_din = 1'b1;
#70
i_din = 1'b0;
#10
i_din = 1'b1;
#20
i_din = 1'b0;
#130
i_din = 1'b0;
#50
i_din = 1'b1;
#140
i_din = 1'b0;
#220
i_din = 1'b1;
#130
i_din = 1'b0;
#1000
$stop();
end
always #5 i_clk=~i_clk;
endmodule
00_006m4. Complete algorithm code file
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