m FPGA-based 4FSK modem system verilog implementation, including testbench test files

Table of contents

1. Algorithm simulation effect

2. Summary of theoretical knowledge involved in algorithms

2.1. Principles and mathematical formulas

2.2. FPGA implementation process

3.Verilog core program

4. Complete algorithm code file

1. Algorithm simulation effect

vivado2019.2 version was developed, and the simulation results are as follows:

2. Summary of theoretical knowledge involved in algorithms

Four frequency shift keying (4FSK) is a commonly used digital modulation method with high frequency band utilization and anti-interference performance. It uses different frequencies to transmit binary data and is usually used in fields such as wireless communications and data transmission.

2.1. Principles and mathematical formulas

The basic principle of 4FSK modulation is to convert input binary data into signals of different frequencies to achieve data transmission. Demodulation is to restore the received signals of different frequencies to the original binary data.

In 4FSK modulation, the input binary data is divided into two groups, each group has two bits. Based on the values of these two bits, the corresponding frequency output is selected. Specifically, there are four frequencies f1, f2, f3, and f4 corresponding to them. Each frequency represents a binary combination (00, 01, 10, 11), that is, 0, 1, 2, 3 in decimal.

Frequency selection: Select the corresponding frequency output according to the input bit combination. For example, when the input is "00", frequency f1 is selected; when the input is "01", frequency f2 is selected; when the input is "10", frequency f3 is selected; when the input is "11", frequency f4 is selected.
Modulated signal: Amplitude modulates the selected frequency to have better anti-interference performance during transmission. Amplitude modulation is usually performed using methods such as on-off keying (OOK) or pulse amplitude modulation (PAM).
Demodulated signal: At the receiving end, signals of different frequencies are demodulated. The required frequency signal is first extracted through a band-pass filter, and then restored to the original binary data through a demodulator. Demodulation methods usually use coherent demodulation or non-coherent demodulation.

2.2. FPGA implementation process

The implementation process of the 4FSK modulation and demodulation system based on FPGA is as follows:

Input data stream: First, the input binary data stream is divided into two groups of two bits each. A clock signal can be used to synchronize the input of data.
Frequency selection: Select the corresponding frequency output based on the value of each group of two bits. A 4-input MUX can be used to implement the frequency selection function. Select the corresponding frequency output signal according to the input bit combination.
Transmit signal: Send the modulated signal through the transmitter. During this process, some filters and other signal processing modules may need to be added to optimize transmission performance.
Receive signal: At the receiving end, after receiving the signal, the required frequency signal is first extracted through the filter. This process can be implemented through digital filters on the FPGA.
Demodulate signal: Send the filtered signal to the demodulator for demodulation. The demodulation function can be implemented using relevant modules in Verilog. For example, the demodulated bit value is determined by detecting the rising and falling edges of the pulse signal.

By combining the high speed and parallelism characteristics of FPGA with 4FSK modulation and demodulation technology, a high-speed and efficient digital communication system can be realized. This implementation method has broad application prospects and can be applied to fields such as wireless communications, data transmission, and the Internet of Things.

3.Verilog core program

The system RTL structure is as follows:

`timescale 1ns / 1ps
//
 
//

module FSK(
input i_clk,
input i_rst,
input[1:0]i_bits,
output signed[15:0]o_carrier1,
output signed[15:0]o_carrier2,
output signed[15:0]o_carrier3,
output signed[15:0]o_carrier4,
output signed[15:0]o_fsk,
output  signed[31:0]o_de_fsk1,
output  signed[31:0]o_de_fsk2,
output  signed[31:0]o_de_fsk3,
output  signed[31:0]o_de_fsk4,
output [1:0]o_bits
);


//调制
FSK_mod FSK_mod_u(
.i_clk     (i_clk),
.i_rst     (i_rst),
.i_bits    (i_bits),
.o_carrier1(o_carrier1),
.o_carrier2(o_carrier2),
.o_carrier3(o_carrier3),
.o_carrier4(o_carrier4),
.o_fsk     (o_fsk)
);
    
    
解调//解调//解调//解调//解调//解调//解调//解调//解调//解调//解调//解调//解调
FSK_demod FSK_demod_u(
.i_clk(i_clk),
.i_rst(i_rst),
.i_fsk(o_fsk),
.o_de_fsk1(o_de_fsk1),
.o_de_fsk2(o_de_fsk2),
.o_de_fsk3(o_de_fsk3),
.o_de_fsk4(o_de_fsk4),
.o_de_ffsk1(),
.o_de_ffsk2(),
.o_de_ffsk3(),
.o_de_ffsk4(),
.o_bits(o_bits)
);
    
endmodule
00_047m