m FPGA-based Gaussian white noise channel simulation system verilog implementation, including testbench, can be configured with different SNR and frequency offset

Table of contents

1. Algorithm simulation effect

2. Algorithms involve an overview of theoretical knowledge

3.verilog core program

4. Complete algorithm code file

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1. Algorithm simulation effect

The simulation results of vivado2019.2 are as follows:

SNR=0db, no frequency offset

SNR=5db, no frequency offset

SNR=25db, no frequency offset 

SNR=45db, with frequency offset 

2. Algorithms involve an overview of theoretical knowledge

       Gaussian white noise channels are of great significance in communication systems, and simulating such channels can help evaluate system performance. The FPGA implementation system proposed in this paper can flexibly simulate different channel conditions and provide strong support for the design and testing of communication systems.

The design of this system is divided into the following steps:

1. Generate Gaussian white noise: Use a random number generator to generate random numbers that obey the Gaussian distribution as a noise signal.
2. Generate sending signal: Generate sending signal according to the application scenario, such as modulated signal.
3. Add channel effect: Add the transmitted signal and Gaussian white noise to simulate the channel effect.
4. Frequency offset simulation: pass the transmitted signal through the frequency offset module to introduce the frequency offset effect.
5. Write Testbench: Write a Verilog test bench, configure different SNR and frequency offset parameters, and verify system functions.

       This system is widely used in communication system design, performance evaluation and algorithm verification. By simulating different channel conditions, the performance of the system in various environments can be evaluated to guide system design optimization. 

3.verilog core program

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2023/08/17 14:13:20
// Design Name: 
// Module Name: TEST
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module TEST();
    
reg i_clk;
reg i_rst;
reg signed[7:0]i_SNR;//根据质量得到当前帧类型:-10~50
reg signed[15:0]i_fre;
wire signed[15:0]i_real1;
wire signed[15:0]i_imag1;
wire signed[15:0]o_Rnoise1;
wire signed[15:0]o_Inoise1;
wire signed[15:0]o_real1;
wire signed[15:0]o_imag1;    
    
reg signed[1:0]i_Idiff;
reg signed[1:0]i_Qdiff;    
initial
begin
    i_Idiff = 2'b00;
    #1440
    repeat(12500)
    begin
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b01;
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b11;
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b11;
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b11;
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b01;
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b01;
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b11;
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b01;
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b11;
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b01;
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b01;
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b01;
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b01;
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b11;
    #10 i_Idiff = 2'b00;
    #30 i_Idiff = 2'b11;
    end
    $stop();
end

initial
begin
    i_Qdiff = 2'b00;
    #1440
    repeat(12500)
    begin
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b11;
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b11;
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b01;
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b01;
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b01;
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b01;
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b11;
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b11;
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b11;
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b01;
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b11;
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b01;
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b11;
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b01;
    #10 i_Qdiff = 2'b00;
    #30 i_Qdiff = 2'b11;
    end
    $stop();
end
    
//测试信号源
wire signed[1:0] w_Inz=i_Idiff;
wire signed[1:0] w_Qnz=i_Qdiff;

//成型滤波
fiter uut1(
.i_clk  (i_clk),
.i_rst  (i_rst),
.i_din  (w_Inz),
.o_dout (i_real1)
);

fiter uut2(
.i_clk  (i_clk),
.i_rst  (i_rst),
.i_din  (w_Qnz),
.o_dout (i_imag1)
);
    
 
initial
begin
    i_clk = 1'b1;
    i_rst = 1'b1;
    i_fre= 0;
    i_SNR = 8'd0;
    #1600
    i_rst = 1'b0;
    i_SNR = 0;
    i_fre= 0;
    #10000
    i_SNR = 5;
    i_fre= 0;
    #10000
    i_SNR = 15;
    i_fre= 0;
    #10000
    i_SNR = 25;
    i_fre= 0;
    #10000
    i_SNR = 45;
    i_fre= 10;//1/2^15*100e6=3k频偏
end

always #5 i_clk=~i_clk;  
    
AWGN_tops AWGN_tops_u(
.i_clk     (i_clk),
.i_rst     (i_rst),
.i_SNR     (i_SNR),//根据质量得到当前帧类型:-10~50
.i_fre     (i_fre),
.i_real1   (i_real1),
.i_imag1   (i_imag1),
.o_Rnoise1 (o_Rnoise1),
.o_Inoise1 (o_Inoise1),
.o_real1   (o_real1),
.o_imag1   (o_imag1)
);  
    
    
    
endmodule
00_037m

4. Complete algorithm code file

V