1. Software version
quartusii 12.1
2. Theoretical knowledge of this algorithm
The basic structure of this system, we follow the structure you provided, the whole block diagram is as follows:
The functions of each section are as follows:
- The encryption algorithm module adopts XOR operation, which performs XOR operation between the binary number sequence encoded by the source and the cipher sequence to generate the ciphertext sequence. After the encryption is completed, the drive system is notified to iterate again, so that the integrity of the data can be guaranteed.
- The main function of the drive system sequence cipher generation module is to generate cipher sequences for encryption. It is the core part of the encryption reliability in the digital encryption system, including the generation of the secret sequence (encrypting the plaintext at the sender.) Because it is a self-synchronizing system, the encrypted chaotic sequence is also used as the iterative value of the driving system.
- The decryption algorithm module also uses the XOR operation. At the receiving end, the ciphertext sequence and the ciphertext sequence are XORed to restore the binary plaintext sequence.
- The password synchronization detection module mainly generates a password synchronization signal to drive the response system password generator module to update the state of the receiver's password generator. Its working principle is to judge whether the ciphertext transmitted through the channel changes, and if it changes, a driving signal is generated. On the one hand, it drives the response system to perform the next iteration, and on the other hand, it drives the decryption algorithm module to decrypt.
- The main function of the response system sequence generator module is to generate a password sequence for encryption. When it receives the password synchronization drive signal generated by the password synchronization detection module, the response system iterates once.
3. Core code
//`timescale 1 ns/ 100 ps
module Encryption_complete_system(
i_clk,
i_rst,
i_enable,//the enable of signal
i_voice, //the signal
o_enable,//the enable of p2s
o_serial_dout,//the serial data of signal
o_serial_frame,
o_T_signal//the data of Encryption
);
input i_clk;
input i_rst;
input i_enable;
input[15:0] i_voice;
output o_enable;
output o_serial_dout;
output o_serial_frame;
output signed[31:0]o_T_signal;
//change the parallel data to serial data
p2s p2s_u(
.i_clk (i_clk),
.i_rst (i_rst),
.i_enable (i_enable),
.i_voice (i_voice),
.o_enable (o_enable),
.o_serial_dout(o_serial_dout)
);
add_frame add_frame_u(
.i_clk (i_clk),
.i_rst (i_rst),
.i_din (o_serial_dout),
.i_enable (o_enable),
.o_dout (o_serial_frame),
.o_enable ()
);
wire signed[31:0]xn;
wire signed[31:0]yn;
wire signed[31:0]zn;
Lorenz Lorenz_u(
.i_clk (i_clk),
.i_rst (i_rst),
.i_yn (o_T_signal),
.o_xn (xn),
.o_yn (yn),
.o_zn (zn)
);
Encryption Encryption_u(
.i_clk (i_clk),
.i_rst (i_rst),
.i_din (o_serial_frame),
.i_yn (yn),
.o_signal (o_T_signal)
);
endmodule //`timescale 1 ns/ 100 ps
module Decryption_complete_system(
i_clk,
i_rst,
i_rec_signal,
o_dout,
o_dout_sign,
o_peak,
o_peak_enable,
o_peak_dout,
o_enable2,
o_voice_dout
);
input i_clk;
input i_rst;
input signed[31:0] i_rec_signal;
output signed[31:0]o_dout;
output o_dout_sign;
output[6:0] o_peak;
output o_peak_dout;
output o_peak_enable;
output o_enable2;
output[15:0] o_voice_dout;
wire signed[31:0]xn;
wire signed[31:0]yn;
wire signed[31:0]zn;
Lorenz2 Lorenz2_u(
.i_clk (i_clk),
.i_rst (i_rst),
.i_yn (i_rec_signal),
.o_xn (xn),
.o_yn (yn),
.o_zn (zn)
);
Decryption Decryption_u(
.i_clk (i_clk),
.i_rst (i_rst),
.i_din (i_rec_signal),
.i_yn (yn),
.o_signal(o_dout)
);
reg o_dout_sign;
always @(posedge i_clk or posedge i_rst)
begin
if(i_rst)
begin
o_dout_sign <= 1'b0;
end
else begin
if(o_dout < 32'h0000_00ff)
o_dout_sign <= 1'b0;
else
o_dout_sign <= 1'b1;
end
end
find_frame find_frame_u(
.i_clk (i_clk),
.i_rst (i_rst),
.i_din (o_dout_sign),
.o_peak (o_peak),
.o_dout (o_peak_dout),
.o_enable(o_peak_enable)
);
s2p s2p_u(
.i_clk (i_clk),
.i_rst (i_rst),
.i_enable (o_peak_enable),
.i_serial_din (o_peak_dout),
.o_enable (o_enable2),
.o_voice_dout (o_voice_dout)
);
endmodule clc;
clear;
close all;
N = 50000;
x = zeros(N,1);
y = zeros(N,1);
z = zeros(N,1);
x(1) = 0.001;
y(1) = 0.002;
z(1) = 0.02;
S1 = double(rand(N,1)>=0.5);
%简化后的发送
for n = 1:N-1
n
%反馈
if n == 1
S1_T(n)= S1(n) + y(n);
y(n+1) = 0.028*x(n) - 0.001*x(n)*z(n) + 0.999*y(n);
x(n+1) = 0.99*x(n) + 0.01*y(n);
z(n+1) = 0.001*x(n)*y(n) + 0.9973333*z(n);
else
S1_T(n)= S1(n) + y(n);
y(n+1) = 0.028*x(n) - 0.001*x(n)*z(n) + 0.999*S1_T(n);
x(n+1) = 0.99*x(n) + 0.01*S1_T(n);
z(n+1) = 0.001*x(n)*S1_T(n) + 0.9973333*z(n);
end
end
%简化后的接收
for n = 1:N-1
n
%反馈
S1_R(n)= S1_T(n) - y(n);
y(n+1) = 0.028*x(n) - 0.001*x(n)*z(n) + 0.999*S1_T(n);
x(n+1) = 0.99*x(n) + 0.01*S1_T(n);
z(n+1) = 0.001*x(n)*S1_T(n) + 0.9973333*z(n);
end
figure;
subplot(311);
plot(S1);
title('原信号');
axis([1,N,-1,2]);
subplot(312);
plot(S1_T);
title('加密后的信号');
subplot(313);
plot(S1_R);
title('解密后的信号');
axis([1,N,-2,2]);
4. Operation steps and simulation conclusion
First, the simulation of the algorithm using MATLAB is implemented. The simulation results we get are as follows:
Run the MATLAB program:
This is the basic simulation of the chaos model, which shows the correctness of the formula and the selection of the initial value.
Run the MATLAB program:
This program is the MATLAB floating-point simulation result graph of the chaotic encryption modulation and demodulation system, which shows that the above results are correct.
Run the MATLAB program:
It can be seen from the above simulation results that if the fixed-point simulation is performed, as long as the quantization width meets certain requirements, it will not affect the accuracy of the system at all.
According to the above introduction, we can write the following program:
From top to bottom, in order:
system top-level file
——Encryption modulation module
——Encryption sub-module, lorenz chaotic sequence generation module, framing module, parallel-serial module.
- Decryption and demodulation module
——Decryption sub-module, Lorenz chaotic sequence generation module, frame search module, serial-parallel module.
The simulation results are as follows:
The pins of the top-level file are:
| 1 |
i_clk |
The system clock is the crystal oscillator position connected to the hardware board. |
| 2 |
i_rst |
System reset, just connect to the key number button on the board. |
| 3 |
o_signal_enable |
Test the generation enable signal of the parallel signal, without connecting the board, |
| 4 |
o_signal |
Test the parallel signal, this signal can be connected to signaltapII for verification |
| 5 |
o_enable |
The enable signal of the encryption module, no need to connect the board |
| 6 |
o_serial_dout |
Serial output, connect to the test pins on the board or signaltapII |
| 7 |
o_serial_frame |
Serial signal framing output, connected to the test pins on the board or signaltapII |
| 8 |
o_T_signal |
Encrypted output, this signal for verification, you can connect to signaltapII |
| 9 |
o_dout |
Decrypted output can be connected to signaltapII |
| 10 |
o_dout_sign |
Decrypt the symbol judgment of the output signal, connect to the test pin on the board or signaltapII |
| 11 |
o_peak |
Correlation peak output of frame search module, no need to connect the board |
| 12 |
o_peak_enable, |
The enable output of the frame search module, no need to connect the board |
| 13 |
o_peak_dout |
The data output of the frame search module is connected to the test pins on the board or signaltapII |
| 14 |
o_enable2 |
The last serial-to-parallel conversion enable, no need to connect the board |
| 15 |
o_voice_dout |
The data output of the final serial-parallel conversion is connected to the test pins on the board or signaltapII |
5. References
[1] Ma Zaiguang, Wu Chunying, Qiu Shuisheng. New Progress and New Attempts in Chaos Synchronization and Chaos Communication Research [J]. Journal of Radio Wave Science, 2002, 17(3):8.
A01-53
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