Table of contents
1. Algorithm simulation effect
2. Algorithms involve an overview of theoretical knowledge
4. Complete algorithm code file
1. Algorithm simulation effect
The system has been developed on two platforms, namely:
Vivado2019.2
Quartusii18.0+ModelSim-Altera 6.6d Starter Edition
The Vivado2019.2 simulation results are as follows:
The test results of Quartusii18.0+ModelSim-Altera 6.6d Starter Edition are as follows:
2. Algorithms involve an overview of theoretical knowledge
QPSK is a digital modulation scheme that maps two binary bits onto a symbol such that each symbol represents four possible phase states. Therefore, the QPSK modulation and demodulation system can achieve higher transmission rate and higher spectral efficiency. The FPGA-based QPSK modulation and demodulation system usually consists of the following modules:
Data Generation Module: Generates the binary data stream to be transmitted.
QPSK modulation module: converts the binary data stream into a sequence of symbols, and maps each symbol to a specific phase state.
QPSK demodulation module: demodulates the received symbol sequence into a binary data stream.
The principle and implementation method of each module will be introduced in detail below.
QPSK Modulation Module
The QPSK modulation module converts a binary data stream into a sequence of symbols and maps each symbol to a specific phase state. QPSK modulation uses four phase states, 0 degrees, 90 degrees, 180 degrees, and 270 degrees. In QPSK modulation, each symbol represents two bits, so the rate of the input binary data stream must be twice the symbol rate.
The QPSK modulation block is usually implemented using a quadrature modulator (I/Q modulator) with sine and cosine outputs. In an I/Q modulator, the input signal is split into two paths, one is called the "quadrature (I) way" and the other is called the "quadrature (Q) way". Each input symbol is mapped to a specific quadrature signal, and then the two signals are added by a combiner to form a QPSK modulated signal.
QPSK demodulation module
The QPSK demodulation module demodulates the received symbol sequence into a binary data stream. The demodulation module is implemented using a coherent demodulator, which can decompose the received signal into two quadrature components, and then multiply them with the local quadrature signal to obtain the original QPSK symbols. The output of the demodulator is a complex number that requires amplitude and phase demodulation to get the original binary data stream.
The development process of FPGA-based QPSK modulation and demodulation system.
First, you need to choose a suitable FPGA platform and development tools. Commonly used FPGA platforms include Xilinx and Altera, and development tools include Vivado and Altera Quartus. Choosing an FPGA platform and development tools requires consideration of system requirements and developer experience.
System Design
System design includes determining system functions, module division and interface design. In the QPSK modulation and demodulation system, it is necessary to determine the function and interface of each module, and determine the direction and rate of data flow. During the design process, factors such as system performance, resource occupation, and delay need to be considered.
Module implementation is the core part of FPGA-based QPSK modulation and demodulation system development. During the implementation of the module, codes need to be written in hardware description language (HDL) and verified using simulation tools. The commonly used HDL languages are VHDL and Verilog, and the simulation tools include ModelSim and ISE Simulator.
FPGA-based QPSK modulation and demodulation system is an efficient and reliable digital communication system. By using the FPGA platform and hardware description language, a QPSK modulation and demodulation system with high performance, low delay and low power consumption can be realized. During the development process, factors such as system functions, performance, resource occupation, and delay need to be considered. System testing can ensure the correctness and reliability of the system.
3. Verilog core program
`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 2023/05/03 05:57:40
// Design Name:
// Module Name: TQPSK
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module TQPSK(
input i_clk,
input i_rst,
input i_Ibits,
input i_Qbits,
output signed[15:0]o_Ifir,
output signed[15:0]o_Qfir,
output signed[15:0]o_cos,
output signed[15:0]o_sin,
output reg signed[31:0]o_modc,
output reg signed[31:0]o_mods,
output signed[31:0]o_mod
);
wire signed[1:0] w_Inz=(i_Ibits == 1'b1)?2'b01:2'b11;
wire signed[1:0] w_Qnz=(i_Qbits == 1'b1)?2'b01:2'b11;
//成型滤波
fiter uut1(
.i_clk (i_clk),
.i_rst (i_rst),
.i_din (w_Inz),
.o_dout (o_Ifir)
);
fiter uut2(
.i_clk (i_clk),
.i_rst (i_rst),
.i_din (w_Qnz),
.o_dout (o_Qfir)
);
//DDS
wire [9:0]mcos;
wire [9:0]msin;
NCO_Trans NCO_Trans_u(
.i_clk (i_clk),
.i_rst (i_rst),
.i_K (10'd512),
.o_cos (mcos),
.o_sin (msin)
);
assign o_cos={mcos,6'd0};
assign o_sin={msin,6'd0};
//调制QPSK
always @(posedge i_clk or posedge i_rst)
begin
if(i_rst)
begin
o_modc <= 32'd0;
o_mods <= 32'd0;
end
else begin
o_modc <= $signed(o_Ifir)*$signed(o_cos);
o_mods <= $signed(o_Qfir)*$signed(o_sin);
end
end
assign o_mod=o_modc+o_mods;
endmodule
00_008m4. Complete algorithm code file
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