1-bit full adder in Quartus II

1. The principle of half adder and 1-bit full adder

1. Half adder

The so-called half adder refers to a component that performs an addition operation on two binary numbers.
The understanding of the binary half adder is relatively simple, that is, every 2 enters 1, and its truth table is as follows:

2. 1-bit full adder

The full adder just adds one more input, in fact, the principle is the same as the half adder. The truth table of the full adder is as follows:

2. The purpose of the experiment

Through the detailed design of 1-bit full adder, master the two design methods of schematic diagram input and Verilog.
The software is based on quartusII version 13.0, and the development board is based on Intel DE2-115.
A 1-bit full adder can be formed by connecting two half adders and an OR gate, so the design of the half adder needs to be completed first.

3. Design a half adder

1. Create a new project

1. file-> new Project WizardSelect project directory, project name, top level file

2. Select the corresponding chip model
   

3. select emulation
   

4. next->finsh

2. Create the schematic

1. file->new-> Block Diagram/Schematic File->OK
   

2. Click the button Symbol Toolor directly double-click the blank space of the schematic diagram
   

3. Select the desired symbol from the Symbol window, or directly type the component name in the name text box
   

4. Call the components and2, xnor and input and output pins input and output respectively. And connect the circuit by clicking and dragging as shown in the figure. Enter the names of the pins: a, b, co and s.
   

5. save, compile
   

6. Set the design item as a callable component
   In order to form the item-level design of the full adder, the half adder half_adder.bdf designed above must be set as a callable component
   file-> Create/Update->Create Symbol Files For Current File
   

3. Half adder simulation

1. select file-> new-> University Program VWF->OK

2. Select the pin number and select in turn
   

3. Run after setting high and low levels
   

4. Running will report an error
   

5. select- Tools>Launch Simulation Library Compiler
   

6. Select the modelSim installation path, select the chip type, select the library language, and select the output file path
   

7. If 0 warnings appear, the compilation is successful

8. Set the waveform again, run, and observe the waveform
   

4. Design a full adder

1. Create a new schematic full_adder and set it as the top-level file
   

2. Call the previously designed half adder element to design the schematic diagram of the full adder
   

3. simulation test
   

5. Hardware download test

1. Pin binding

Before pin binding, it is necessary to determine the specific hardware circuit, that is,
the connection between the target chip and the peripheral circuit (input, output display, etc.). The ED2-115 development board used in the laboratory, in addition to the core FPGA chip, also has
some peripheral input and output circuits. We use these input and output circuits for hardware testing.

If the pins of the full adder are bound, it can be designed as follows: select three of the 18 DIP switches on the development board, and
SW0, SW1, and SW2 are connected to ain, bin, and cin respectively (pull the switch up and down to display the input
is high or low level); LED0, LED1 are respectively connected to co and sum, the light on means the output is "1", and the light off
means the output is "0".
After the hardware is designed, you need to check the pin diagram (see the appendix for the pin diagram) for pin binding.
Find the three input switches SW0, SW1, SW2 from the appendix "Table 4-1 Pin Configuration of Toggle Switch"
, and then find the corresponding "FPGA pin number". As shown in the figure:

Correspondingly, find the pin configuration of the LED in Table 4-3 of the appendix.
Then in the software, select "assignments→pin planner" from the menu, as shown in the figure, call out the pin
binding window, then select the corresponding input and output ports from the drop-down window, and then
fill in the corresponding FPGA in the "location" column pins, as shown in the figure.

After the pin is selected, the schematic file must be compiled again to actually bind the pin. After the pins are bound
and the compiled file is shown in the figure,

it can be downloaded to the hardware for testing.

2. Download test

Connect the development board to the power supply, and connect the USB interface to the computer. Turn on the power switch (be sure to turn off the
switch when not downloading, so as not to burn the board). Click the button on the software toolbar,
and the download interface will appear. The first download requires
hardware installation. That is, click the button "hardware setup..." in the download interface, then select "USB blaster" in the pop-up dialog box
, and then click "ok", then the hardware is installed.

The interface of the installed hardware is shown in the figure. Then tick the check box behind the downloaded .sof file, and then click "start".
When the progress bar reaches 100%, the download is successful, and hardware observation can be performed

Result verification

ain	bin	cin	sum	cout
1	1	1	1	1

Six, Verilog language design

1. file->new->Verilog HDL File->OK
   

2. code:

module full_adder1
(
	input a,     	//加数
	input b,		//被加数
	input c,		//进位输入
	output s,		//结果输出
	output co		//进位输出
);
	assign s = a^b^c;
	assign co = (a&b)|((a^b)&c);
endmodule

3. file->Create/Upadte ->Create Aysbol Files For Current Filegenerate schematic diagram
   

4. select schematic
   

5. Add input and output
   

6. simulation test
   

7. Summary

Through the detailed design of 1-bit full adder, mastered the two design methods of schematic diagram input and Verilog.