The specific construction experiment results are as follows:
- Full adder's complement adder/subtractor analog circuit diagram.
Fig.1 Analog circuit diagram of four-bit full-complement adder/subtractor
According to Figure 1 above, the experimental circuit shown in Figure 6.7 is obtained
Figure 2 Design circuit diagram of four-bit full complement code adder/subtractor
Fig. 2 Diagram of design circuit diagram of four-bit full-plus-complement adder/subtractor
The following table 1 is the input and output values of the experimental verification of the correctness of the addition and subtraction of the full complement code
Table 1 Truth table of full-plus-complement adder-subtractor
| enter |
output |
||||||||||||
| A4 |
A3 |
A2 |
A1 |
B4 |
B3 |
B2 |
B1 |
M |
S4 |
S3 |
S2 |
S1 |
carry/sign bit |
| 1 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
1 |
| 0 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
| 1 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
| 0 |
1 |
0 |
1 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
0 |
The screenshot of the output value corresponding to the input result in Table 1 is shown in the figure below.
Input 1010, 1001 addition output result
Input 0000, 1101 addition output result