Implementing a full adder in VHDL

Implementing a full adder in VHDL

1. One-bit full adder The
full adder is a binary addition circuit that can calculate the low-order carry. The logical expression of one-bit full adder (FA) is:
F=A⊕B⊕Ci
Co=Ci(A⊕B)+ AB
where A, B are the numbers to be added, Ci is the carry input; F is the sum, and Co is the carry output. The
truth table is as follows: The

schematic diagram is as follows:

Therefore, when designing the entity, three inputs and two outputs are selected:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED;
ENTITY homework5 IS
	PORT(
		a,b,ci:IN STD_LOGIC;
		f,co:OUT STD_LOGIC
	);
END homework5;
ARCHITECTURE yejiayu OF homework5 IS
BEGIN
	f<=(a XOR b)XOR ci;               --F=A⊕B⊕Ci
	co<=((a XOR b)AND ci)OR(a AND b); --Co=Ci(A⊕B)+AB
END yejiayu;

The simulation after saving and compilation is as follows:

2. Four-bit full adder

(1) Component instantiation method implementation:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY	homework6 IS
	PORT(
	A0,A1,A2,A3,B0,B1,B2,B3:IN STD_LOGIC;
	F0,F1,F2,F3:OUT STD_LOGIC;
	CI:IN STD_LOGIC;
	CO:OUT STD_LOGIC
	);
END homework6;
ARCHITECTURE yejiayu OF homework6 IS
COMPONENT homework5						--COMPONENT语句来实现元件例化方法
	PORT(
	a,b,ci:IN STD_LOGIC;
	f,co:OUT STD_LOGIC
	);
END COMPONENT homework5;
SIGNAL S0,S1,S2:STD_LOGIC;
BEGIN
	U1:homework5 port map(A0,B0,CI,F0,S0);
	U2:homework5 port map(A1,B1,S0,F1,S1);
	U3:homework5 port map(A2,B2,S1,F2,S2);
	U4:homework5 port map(A3,B3,S2,F3,CO);
END yejiayu;

Among them, homework5 is the entity file of the full adder above
(pay attention next!!!)
First, open quratusII and click to open the homework5 file

Then create a new VHDL file, write the four-bit full adder code, save it to the same folder (must be in the same folder!!!) and

then click the settings button to change the order before compiling (otherwise I would have fallen behind when compiling homework5 Here)


select homework6

and then compile and simulate

(2) Simplify the implementation
of a 4-bit full adder Design a 4-bit full adder by calling the "+" method in the STD_LOGIC_UNSIGNED package. The
code is as follows:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY homework7 IS
PORT(
	A,B:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
	F:OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
END homework7;
ARCHITECTURE yejiayu OF homework7 IS
BEGIN
PROCESS(A,B)
BEGIN
	F<="00000"+A+B;
END PROCESS;
END yejiayu;

Compile and simulate:

ᵎ(•̀㉨•́)و ̑̑ Come on