Quartus II 13.1 Installation
1. Download
Punctual Atomic Baidu Cloud: https://pan.baidu.com/s/1a9d-bq9RZmWrRV542X4IEA
Extraction code:
ifte
2. Installation
After decompression, double-click to install:
Next：
accept，Next：
Choose the installation location, Next:
Next:
Next：
Finish：
OK：
3. Registration and driver installation
Registration file:
https://pan.baidu.com/s/16GnGbr4v-EFKF0VZYUArsg
Extraction code:
766d
Installation and use from Quartus II 13.1
Put the downloaded registry Quartus_13.1_x64.exefile in Quartus-llthe installation path ..\quartus\bin64 下, and double-click to execute:
应用:
保存：
退出：
Open the software:
Choose the second one, OK:
Click on Toolsthe following License Setup…:
Copy a NIC at will:
Replace license.datin XXXXXXXXXXXX:
After replacing:
Re-open the software and find that the date has changed:
Connect one end of the USB cable to the downloader, and the other end to the USB port of the computer.
Open Device Manager:
Right click USB-Blaster, 更新驱动程序软件:
浏览我的计算机以查找驱动程序软件：
select ...\qurtus\drivers\usb-blaster, 下一步:
安装：
Successful installation:
4. Use
1. New construction
New:
Next：
Fill in the project directory and project name Next:
No need to add existing engineering design files, directly Next:
Select the corresponding chip, Next:
Next：
Finish：
Created successfully:
2. Create a new schematic file
select Block Diagram/Schematic File, OK:
Click 插头图标to search for components and place them on the drawing:
- 1 and 2
- 1 xor
Add two input pins and two output pins, double-click Pin Name to modify the pin name, name the input pin as aand b, and name the output pin as coand s:
Drag the pins to connect:
save document:
Compile:
Compiled successfully:
When open adder.bdf, design the design item as a callable component:
keep:
3. Half adder simulation
New：
select University program VWF, OK:
Select Edit→ Insert→ Insert Node or Bus…:
Click on Node Finder:
List：
Move all ports on the left to the right, OK:
OK：
Set the input waveform value:
Ctrl + S Save:
simulation:
Found an error:
According to the online method, modelisim.exethe location to join:
Compile again and find that an error is still reported:
But the error message is different, this time the cause of the error is 项目文件不能有空格.
So, copy the project to a new folder:
Double-click .qpfthe file to open the project:
OpenOpen the previous .vwf(仿真)file:
After simulation, it is found that an error is still reported:
Solution:
Output directoryBe sure to select the item under simulation\qism:
Open .vwfthe file and simulate again, successfully:
4. Design the top-level file of the full adder
New：
Select Symbole Tool, search adder, i.e. the previous half adder:
Together with other elements, a full adder is formed:
- two half adders
- a or2
- three inputs
- 2 outputs
Ctrl + S save as full_adder.bdf:
Make this a top level file:
Compile and simulate:
5. Pin Binding
select Pin Planner:
Bind the corresponding pins:
Compile again:
6. Burn
Burning:
The first download requires hardware installation. That is, click the button in the download interface hardware setup..., then select in the pop-up dialog box USB blaster, and then click ok, the hardware will be installed:
Start：
Burning is successful:
7. Results
8. Verilog implementation
8.1 Create verilog file
New：
The first line my_fuller_adderneeds to have the same name as your own file:
module my_fuller_adder(
//输入信号，ain表示被加数，bin表示加数，cin表示低位向高位的进位
input ain,bin,cin,
//输出信号,cout表示向高位的进位，sum表示本位的相加和
output reg cout,sum
);
reg s1,s2,s3;
always @(ain or bin or cin) begin
sum=(ain^bin)^cin;//本位和输出表达式
s1=ain&cin;
s2=bin&cin;
s3=ain&bin;
cout=(s1|s2)|s3;//高位进位输出表达式
end
endmodule
Set as top file:
Compile and view the circuit diagram:
8.2 Simulation
8.3 Burning
V. Summary
Verilog writing is very convenient compared to building circuits yourself.
reference
https://stackoverflow.com/questions/28919269/waveform-file-not-running-under-simulation