I wrote an adder in Quartus II 13.1, the program is as follows
`timescale 1ns/1ns
module Counter_Design
(
//global clock
input clk, //50MHz
input rst_n,
//user interface
output reg [3:0] cnt
);
//----------------------------
//Counter for 4 bit data
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
cnt <= 0;
else
cnt <= cnt + 1'b1;
end
endmodule
The resulting RTL view is as follows:
In the adder, the value of cnt should be incremented by one each time, but in the RTL view, B[3:0] is 4'h8, I thought it should be 4'h1. Later, after careful observation, it was found that by clicking on the B[3:0] attribute on the left side of the RTl view, it was found that the B[0] bit is high, and the other bits are low. Therefore, it is inferred that B should be a selection signal here, not cnt to be added. Number, 4'h8 of B[3..0] just selects the 0th bit of cnt plus 1.