RTL Basics: Full Adder Design (VHDL)

【Design requirements】

Using the hierarchical design method, the four-bit binary full adder is designed and simulated in VHDL language.

【aim of design】

Check your familiarity with VHDL component instantiation syntax;

Examine your understanding of how full adders work in digital circuits;

【Design ideas】

A combination circuit that uses a gate circuit to add two binary numbers and find the sum is called a one-bit full adder. A one-bit full adder can handle the low-order carry and output the carry-in-place addition. A multi-bit full adder can be obtained by cascading multiple one-bit full adders.

The first step: a full adder;

The second step: a multi-bit full adder, in which a one-bit full adder is instantiated;

1 bit full adder

a and b are two bits of binary data, cin is the carry bit of the previous stage, cout is the carry bit after the current calculation, sum is the addition result, the circuit structure and truth table are as follows:

 

2 Four-bit full adder

The four-bit full adder is implemented by serial cascading with carry on the basis of one-bit full adder. The schematic diagram of the circuit structure after implementation is as follows:

 

【Source code】

1-bit full adder source code

 

2 Four-bit full adder source code

 

【Experiment result】

 

【think】

During simulation, there may be glitches in the input. What method can be used to eliminate the glitches?

When designing a multi-bit full adder, if the number of bits is large, the program will be very long in the way of component instantiation. What methods can be used to improve the implementation?