You can refer to the following link and combine my article steps to learn (my details haha~)
Zero, basic use of Quartus II (group experiment) 
https://blog.csdn.net/qq_40925617/article/details/121171310?spm= 1001.2014.3001.5502
1. Create a project, design a full adder, and simulate it
Graphic Design Circuit Diagram: Full Adder
A logic circuit that can add two 1-bit binary numbers and consider the carry from the lower order (that is, equivalent to the addition of 3 1-bit binary numbers) to obtain "sum" and "carry" is called a full adder. A and B are the input of two 1-bit binary numbers respectively; Cin is the carry input from the low order; S and Cout are the "sum" formed by addition and the "carry" output to the high order.
1. New construction FA
2. Save the location D:\IT\Quartus\FA
Project name FA
Main file (top-level design entity) FA
3. New - Block Diagram, save as FA
Design schematic files are saved as FA.BDF
4. Save the design schematic file as FA.BDF
(1) Add components:
Input signal: input , output signal: output , 2 AND gate: and2 , 2 OR gate: or2 , XOR gate: xor
Modify the input signal to be A, B, Cin in sequence, and the output signal to be S, Cout in sequence
(2) Connecting components: No need to point the line, just drag the mouse on the line head and drag it directly
5. Compilation: Click Start Ccompilation
Note: It prompts that the interface is compiled successfully. If the compilation is wrong, it may be that your drawing is wrong. The main reason is that there is a problem with the line you connected, and it is twisted and knotted!
6. Design Simulation Waveform File
New - Vector Waveform File
7. Insert the simulated signal (shortcut menu - insert node or bus - node finder)
8. Ctrl+S save, name FA
Be sure to name the same, don't ask why, if you don't listen, you will be asking for trouble if you compile it wrong!
9. Set A as the clock signal of 40ns and end time as 40ns
Set B to 20ns clock signal and end time to 40ns
Set Cin to 10ns clock signal and end time to 40ns
10. Processing - simulation tools
11. Select - functional to perform functional simulation (generate a netlist file for functional simulation)
Start - start simulation
Report - View simulation results
12. Use the schematic file FA.bdf to create the symbol file FA.bsf
文件——Create/Update——Create Symbol File for Current File
2. Establish a project, design an 8-bit traveling-wave carry adder, and simulate it
Graphic Design Circuit Diagram: 8-Bit Traveling-Wave Carry Adder
The traveling wave carry adder connects n-bit full adders in series, and the carry output of the low-order full adder is connected to the carry input of the adjacent high-order full adder. The high-order bits are transmitted step by step, like a traveling wave. The high-order sum cannot be determined until the low-order carry is formed. Finally, the carry of the highest order and the carry of the sign bit are XORed, and the information of whether overflow can be obtained.
1. New project adder8
Save locationD:\IT\Quartus\adder8
Project name adder8
main file (top-level design entity) adder8
2. Copy the FA project to the adder8 directory
3. New - Block Diagram, save as adder8
4. Add component FA
Input signal, output signal, FA, XOR gate xor
Modify the input signals to be A[7..0], B[7..0], C0
Modify the output signals to be S[7..0], C8, Overflow
Connecting elements:
When connecting, in order to specify which signal in the connected bus, it is necessary to set the connection corresponding to a signal, such as: A[0]
teacher's reference
Reference drawings drawn by yourself
5. Compile
6. Design Simulation Waveform File
New - Vector Waveform File
7. Insert the simulated signal (shortcut menu - insert node or bus - node finder)
A、B、C0、 S、C8、Overflow
8. Set C0 to 0, A and B are random values that change once per half clock
(The random value needs to include various situations that may occur, and if it is not suitable, a value can be manually modified)
A, B, S are displayed as Signed Decimal (signed numbers)
9. Save the file - save it as adder8.vwf
10. Processing - simulation tools
Select -- functional to perform functional simulation, (generate a netlist file for functional simulation)
Start - start simulation
Report - View simulation results
11. Perform analysis
The above is about the operation steps of the experiment. Self-study early, don't wait until class to listen to the teacher's lecture, the efficiency is too low, since no one has written about this part of the operation on the Internet, I will work hard to serve everyone!