one bit full adder
In the process of designing a full adder, the following two issues need to be considered:
- how to generate the sum of added numbers
- How to generate the carry digit of the added number
Logical implementation of sum numbers
The sum is 1: 0 + 1 = 1 1 + 0 = 1 The sum is 0: 0 + 0 = 0 1 + 1 = 0 The sum is 1: 0 + 1 = 1 \space \space 1 + 0 = 1 \\The sum is 0: 0 + 0 = 0 \space \space 1 + 1 = 0sum to 1:0+1=1 1+0=1sum to 0:0+0=0 1+1=0
According to the above formula, it can be known that an XOR gate can be used to automatically realize one-bit addition (convert arithmetic operation into logical operation), and the circuit that realizes this simple function is called Half Adder HA (Half Adder ) .
The corresponding formula is:
S = X ⨁ YS=X\bigoplus{Y}S=X⨁Y
Logical implementation of carry digits
On the basis of realizing the sum logic circuit, consider the realization of the carry number:
According to the above table, when there is an odd number of 1s in the two addends and the low-order carry digit, and the sum is 1, it can also be realized with the help of an XOR gate, and the case where the carry digit is 1 can be analyzed according to the source of the carry, that is Either the two addends are 1, or one of the addends is 1, and the lower carry digit is also 1, so the following formula can be obtained:
S i = X i ⨁ Y i ⨁ C i C i + 1 = X i Y i + ( X i ⨁ Y i ) C i S_{i}=X_{i}\bigoplus{Y_{i}}\bigoplus{C_{i}} \\C_{i+1}=X_{i} Y_{i}+(X_{i}\bigoplus{Y_{i}})C_{i}Si=Xi⨁Yi⨁CiCi+1=XiYi+(Xi⨁Yi)Ci
According to the above analysis, the logic implementation of a full adder can be designed:
Its internal circuit implementation can be:
