introduction:
Finite state machine and its design technology are an important part of practical digital system design and an important way to realize high efficiency, high reliability and high-speed control logic system.
Broadly speaking, as long as it is a circuit involving flip-flops, no matter the size of the circuit, it can be attributed to a state machine. Therefore, for digital system design engineers, as long as they are faced with sequential circuit design, the concept of state machine is the most basic design idea and design method that must run through the entire design.
The HDL expression form and expression style of the state machine based on modern digital system design technology has a certain typicality and regularity. As long as you grasp these fixed sentence expression parts, you can write various Verilog state machines in different styles and for different practical purposes according to actual needs.
The structure of a general finite state machine:
1) Description part (state transition variable definition and description of all possible states)
In the description part of the Verilog state machine program, each state element (such as s0, s1) is defined by the parameter description keyword parameter. The specific value or code taken by each status element must be written, and the bit width description next to the keyword [2:0] can be written or not.
parameter [2:0] s0=0, s1=1,s2=2,s3=3,s4=4;
reg[2:0] cuurent_srate,next_state;
Syntax: parameter definition keyword parameter
Using the keyword parameter to define a constant is to use parameter to define an identifier to represent a constant, such as the delay, the width of the variable, and so on. This method can easily change the entire design.
format:
parameter identifier 1= expression or value 1, identifier 2= expression or value 2,...;
E.g:
parameter A=15，B=4‘b1011，C=8’hAC
The constant defined by the parameter in the module can only be assigned once.
2) Master control sequence process
The so-called master control sequence process refers to the process responsible for the operation of the state machine and the state transition driven by the clock. The state machine works with an external clock signal in a synchronous timing mode.
3) Master control combination process
If the state machine is likened to a machine tool, then the master control sequence process is the drive motor of the machine tool, the clk signal is the power wire of the motor, and the master control combination process is the machining part of the machine tool, and its operation depends on The drive of the motor depends on the control of the machine operator.
4) Auxiliary process
The auxiliary process is used to cooperate with the combined process or the sequential process of the state machine. such as:
module FSM_EXP(clk,rst,sin,cout,cstout);
input clk; //状态机时钟
input rst; //复位信号
input [0:1] sin; //来自外部的状态机控制信号
output [4:0] cstout; //状态机对外部发出的控制信号信号输出
output [3:0] cout;
reg [3:0] cout;
assign cstout=cst;
parameter s0=0,s1=1,s2=2,s3=3,s4=4; //定义状态参数
reg[4:0] cst,nst; //当前状态、下一状态
always@(posedge clk or negedge rst) //主控时序进程
begin
if(!rst) cst<=s0; //复位有效时，下一状态进入s0
else cst<=nst;
end
always@(cst or sin)begin //主控组合进程
case(cst)
s0:begin cout<=5;
if(sin==2'b00) nst<=s0;
else nst<=s1;
end
s1:begin cout<=8;
if(sin==2'b01) nst<=s1;
else nst<=s2;
end
s2:begin cout<=12;
if(sin==2'b10) nst<=s2;
else nst<=s3;
end
s3:begin cout<=14;
if(sin==2'b11) nst<=s3;
else nst<=s4;
end
s4:begin cout<=9;
nst<=s0;
end
default:nst<=s0; //现太若未出现以上各太，返回初态s0
endcase
end
endmodule
Experiment content: design of sequence detector
Design requirements:
Use the state machine to realize the design of the sequence detector, and carry on the simulation and hardware test to it.
Design principle:
The sequence detector can be used to detect one or more sets of pulse sequence signals composed of binary codes. When the sequence detector continuously receives a set of serial binary codes, if this set of codes is the same as the code preset in the detector, then Output A, otherwise output B.
Tip 1: Sequence detector components and status values:
Tip 2: The conversion relationship between the states of the state machine
Reference Code:
module FSM(clk,rst,DIN,DOUT);
input clk;
input rst;
input DIN;//输入一位二进制数
reg [7:0] D;//预置数?
output [3:0] DOUT;
reg [3:0] DOUT;
parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7,s8=8;
reg[7:0] CST,NST;//当前状态、下一状态
always@(posedge clk or negedge rst)//主控时序进程
begin
if(!rst) CST<=s0;
else CST<=NST;
end
always@(CST or DIN)begin//主控组合进程
case(CST)
s0:begin DOUT<=4'b1011;
if(DIN==D[7]) NST<=s1;
else NST<=s0;
end
s1:begin DOUT<=4'b0001;
if(DIN==D[6]) NST<=s2;
else NST<=s0;
end
s2:begin DOUT<=4'b0010;
if(DIN==D[5]) NST<=s3;
else NST<=s0;
end
s3:begin DOUT<=4'b0011;
if(DIN==D[4]) NST<=s4;
else NST<=s0;
end
s4:begin DOUT<=4'b0100;
if(DIN==D[3]) NST<=s5;
else NST<=s0;
end
s5:begin DOUT<=4'b0101;
if(DIN==D[2]) NST<=s6;
else NST<=s0;
end
s6:begin DOUT<=4'b0110;
if(DIN==D[1]) NST<=s7;
else NST<=s0;
end
s7:begin DOUT<=4'b0111;
if(DIN==D[0]) NST<=s8;
else NST<=s0;
end
s8:begin DOUT<=4'b1010;
NST<=s0;
end
default:NST<=s0;
endcase
end
endmodule
Note: D[7]--D[0] here needs to be initialized and can be replaced with a string of numbers, such as 11001100;
Simulation waveform:
Tip 3: State hardware verification mode selection
Pin lock:
It is recommended to use key 7 (PIO11) to control the reset signal CLR; key 6 (PIO9) to control the state machine working clock CLK; the serial number input DIN to be detected is connected to PIO10 (left shift, the highest bit is first); the indicator output AB is connected to PIO39～ PIO36 (displayed on digital tube 6). After downloading, 1. Press the "System Reset" button on the experiment board; 2. Use the keys 2 and 1 to input the 2-digit hexadecimal sequence number "11100101" to be tested; 3. Press the 7 to reset (usually the number 6 indicates "B" ”); 4. Key 6 (CLK) 8 times, at this time, if the serially input 8-bit binary serial code (displayed on the digital 2/1 and LED D8～D0) is the same as the preset code "11100101", then the digital 6 should change from the original B to A, indicating that the sequence detection is correct, otherwise it is still B.
Summary and analysis: