Purpose:

Learn the design, analysis and testing methods of the numerical control frequency divider, and practice the design and application of the counter.

Experiment preview:

Familiar with the design of the counter; understand how to use the counter to realize the design of the frequency divider.

Experimental explanation: design of frequency divider

Consider two questions:

Q: What is a frequency divider and what is the frequency division coefficient?

A: The circuit that can convert the high-frequency signal clk into the low-frequency signal clk_1 is called a frequency divider. If the period of the clk_1 signal is n times the period of clk, then n is the frequency division coefficient)

Q: What is the core idea of frequency divider design?

A: The design of the counter)

Design of even divider (take 6 divider as an example)

module dvf6(clk,clk_1);
input	clk;
output	reg	clk_1;
reg[2:0]	q;
always@(posedge	clk)
begin
	if(q==3'b101)	q<=3'b000;
	else	q<=q+1;
end
always@(q)
begin
	if(q>=3b'011)	clk_1<=1'b1;
	else	clk_1<=1'b0;
end
endmodule


另一种设计方案
module dvf6(clk,clk_1);
input	clk;
output	reg	clk_1;
reg[2:0]	q；b
always@(posedge	clk)
begin
	if(q==3'b010)	begin	q<=q+3'b001;  clk_1<=~clk_1;end
	else if	(q==3'b101)	begin q<=3'b000;  clk_1<=~clk_1;end
	else	q<=q+3'b001;
end
endmodule

The design of odd frequency divider (take 9 frequency divider as an example)

module	dvf9(clk,clk_1);
input	clk;
output	clk_1;
reg[3:0]	q1,q2;
reg	clk_p,clk_n;
always@(posedge clk)
begin
	if(q1==4'b100)	begin	q1<q1+4'b0001;clk_p<=~clk_p;end
	else if(q1==4'b1000)	begin	q1<=4'b0000;clk_p<=~clk_p;end
	else	q1<=q1+4'b0001;
end
alway@(negedge clk)
begin
	if(q2==4'b0100)	begin	q2<=q2+4'b0001;clk_n<=~clk_n;end
	else if	(q2==4'b1000)	begin	q2<=4'b0000;clk_n<=~clk_n;end
	 else	q2<=q2+4b'0001;
end
always@(negedge	clk)
begin
	if(q2==4b'0100)	begin	q2<=q2+4'b0001;clk_n=~clk_n;end
	else if(q2==4'b1000)	begin	q2<=4'b0000;clk_n<=~clk_n;end
	else	q2<=q2+4'b0001;
end
assign	clk_1=clk_p|clk_n;
endmodule

30 divider design

module dvf_30(clk,clk_1);
input	clk;
output	reg	clk_1;
reg[4:0]	q;
always@(posedge	clk)
begin
	if(q==5'b11101)	q<=5'b00000;
	else	q<=q+1;
end
always@(q)
begin
	if(q>=4'b1111)	clk_1<=1'b1;
	else	clk_1<=1'b0;
end
endmodule

Experiment content: design of numerical control frequency divider

The function of the numerical control frequency divider is that when different input data is given at the input terminal, the input clock signal will have different frequency division ratios. The numerical control frequency divider is designed with an addition counter whose count value can be preset in parallel. The method is to connect the counting overflow bit with the preset number loading input signal.

Source code

module	dvf_suk(clk,D,fout,full_1);
input	clk;
input	[7:0]	D;
output	reg	fout;
reg[7:0]	reg8;
reg	full;
output full_1;
always@(posedge clk)
begin
	if(reg8==8'hff)	begin	reg8<=D;full<=1'b1; end
	else	begin	reg8<=reg8+8'b1;full<=1'b0; end
end
always@(posedge full)
begin
	fout<=~fout;
end
assign full_1=full;
endmodule

Simulation waveform

Hardware verification

When designing the function of the numerical control frequency divider, you can choose experimental circuit mode 1, in which key 2/key 1 is responsible for inputting the 8-bit preset number D (PIO7~PIO0); CLK is input by clockB0, and the frequency is 65536Hz or higher (to ensure the division After the frequency falls in the audio range); the output is connected to the buzzer signal input terminal. Change the input value of key 2 / key 1, and you can hear sounds of different tones.

after class homework

A circuit is designed using two numerically controlled frequency divider modules, so that the width of the positive and negative pulse width of the square wave output is controlled by two 8-bit input data respectively.

EDA (Quartus II)-Design of CNC Frequency Divider