Preface: The content of this chapter is mainly to demonstrate the circuit design, simulation, synthesis and download using Verilog language under Vivado
Example: Adder
- Features: Using Xilinx Artix-7 XC7A35T chip
- Configuration method: USB-JTAG/SPI Flash
- Up to 100MHz internal clock speed
- Memory: 2Mbit SRAM N25Q064A SPI Flash (the old model of the sample picture is N25Q032A)
- General IO: Switch: x8LED: x16Button: x5DIP: x8 General expansion IO: 32pin
- Audio and video/display: 7-segment digital tube: x8 VGA video output interface Audio audio interface
- Communication interface: UART: USB to UART Bluetooth: Bluetooth module
- Analog interface: DAC: 8-bit resolution XADC: 2-way 12bit 1Msps ADC
Table of contents
Ⅰ. Pre-knowledge
0x00 Half adder
A logic circuit that can add, sum and carry two 1-bit binary numbers is called a half adder . Or: only consider the addition of two one-bit binary numbers, without considering the operation circuit from the low- order carry , called a half-adder.
The following figure is a block diagram of a half adder:
Among them: In1 and In2 are the summand and the addend respectively , which are used as the input terminals of the circuit; S is the standard sum generated by the addition of two numbers, and it is used as the output of the circuit together with the high-order carry C generated by the addition of two numbers.
According to the principle of adding binary numbers, the truth table of the half adder is obtained as follows:
| signal input |
signal output |
||
| In1 | In2 | S |
C |
| 0 |
0 |
0 |
0 |
| 0 |
1 |
1 |
0 |
| 1 |
0 |
1 |
0 |
| 1 |
1 |
0 |
1 |
0x01 Full adder
A full adder is actually an adder that takes carry into account.
| Full adder input |
Full adder output |
|||
| A |
B |
Cin |
BCDout |
Cout |
| 0 |
0 |
0 |
0 |
0 |
| 0 |
0 |
1 |
0 |
1 |
| 0 |
1 |
0 |
0 |
1 |
| 0 |
1 |
1 |
1 |
0 |
| 1 |
0 |
0 |
0 |
1 |
| 1 |
0 |
1 |
1 |
0 |
| 1 |
1 |
0 |
1 |
0 |
| 1 |
1 |
1 |
1 |
1 |
Truth table:
Logical expression:
Since two half adders can form a full adder, the carry Ci here can also be expressed as:
Ⅱ. Verilog implementation
0x00 Precautions
In this experiment, the writing of submodules and main modules is involved .
In the main module (top-level file), the submodule is called to satisfy the design
The following takes the adder as an example to introduce the writing and calling of submodules and main modules:
1. Design sub-modules
Reference program:
Program file one:
module FA1(input A,input B,input Cin,output reg Cout,output reg S);
always @(A or B or Cin)begin
{Cout,S}=A+B+Cin;
end
endmoduleProgram file two: (optional, custom)
module UserAND(a,b,z);
input a,b;
output z;
assign z=a&b;
endmodule The above programs can also be designed and modified by themselves;
2. Design the main module: (top-level file)
module EX5_Top(input [1:0] IA,input [1:0] IB,output [1:0] sum,output C );
wire ct;
//子模块的调用，例如其中FA1为子模块名称，FD0和FD1为在顶层文件中引用的名称。
FA1 FD0 (.A(IA[0]),.B(IB[0]),.Cin(0),.Cout(ct),.S(sum[0]));
FA1 FD1 (.A(IA[1]),.B(IB[1]),.Cin(ct),.Cout(C),.S(sum[1]));
Endmodule3. Compile the file and view the RTL view (as shown in the figure)
0x01 One-bit full adder
Design code:
module ADD_Top(input [1:0] IA,input [1:0] IB,output [1:0] sum,output C );
wire ct;
ADD FD0 (.A(IA[0]),.B(IB[0]),.Cin(0),.Cout(ct),.S(sum[0]));
ADD FD1 (.A(IA[1]),.B(IB[1]),.Cin(ct),.Cout(C),.S(sum[1]));
endmodule
module ADD(input A,input B,input Cin,output reg Cout,output reg S);
always @(A or B or Cin)begin
{Cout,S}=A+B+Cin;
end
endmodule
Simulation design code:
module sim_ADD_Top( );
reg [1:0] IA;
reg [1:0] IB;
wire [1:0] sum;
wire ct;
ADD_Top uu1(IA,IB,sum,ct);
initial {IA,IB}=4'b0000;
always
#100{IA,IB}={IA,IB}+1;
endmoduleClick the "Run Simulation" menu of Vivado to enter the simulation debugging mode, and you can see the simulation timing waveform in the simulation output window
Waveform diagram:
0x02 Serial adder
On the basis of understanding the half adder and full adder, using a modular design method, we can realize the design of a four-bit serial adder through four full adders
Design code:
`timescale 1ns / 1ps
module M_4bit_adder(S,C3,A,B,C_1);
input [3:0] A,B;
input C_1;
output [3:0] S;
output C3;
wire C0,C1,C2;
fulladder u0(S[0],C0,A[0],B[0],C_1);
fulladder u1(S[1],C1,A[1],B[1],C0);
fulladder u2(S[2],C2,A[2],B[2],C1);
fulladder u3(S[3],C3,A[3],B[3],C2);
endmodule
module halfadder(S,C,A,B);
input A,B;
output S,C;
xor(S,A,B);
and(C,A,B);
endmodule
module fulladder(S,C,A,B,Cin);
input A,B,Cin;
output S,C;
wire S1,D1,D2;
halfadder HA1(.S(S1),.C(D1),.A(A),.B(B));
halfadder HA2(.S(S),.C(D2),.A(S1),.B(Cin));
or g1(C,D2,D1);
endmodule
Simulation design code:
module sim_ADD();
reg [3:0] A,B;
wire [3:0] S;
wire C3;
M_4bit_adder uu1(S,C3,A,B,0);
initial {A,B}=8'b0000_0000;
always
#100 {A,B}={A,B}+1;
endmoduleWaveform diagram:
Add hardware constraints and connect the breadboard,
The reference pin assignment is as follows:
| Program pin name |
actual pin |
illustrate |
| A（0） |
N4 |
Toggle switch SW1 |
| A（1） |
M4 |
Toggle switch SW2 |
| B（0） |
R2 |
Toggle switch SW3 |
| B（1） |
P2 |
Toggle switch SW4 |
| SUM（0） |
K2 |
LED 0 |
| SUM（1） |
J2 |
LED 1 |
| C |
J3 |
LED 2 |
Breadboard implementation:
