Let me first talk about the difference between SignalTap and ModuleSim. Obviously, these are two different things. SignalTap is integrated in Quartus II and uses JTAG to capture actual signals for analysis, while ModuleSim is independent of Quartus II. A software used for functional simulation.
Generally speaking, using ModuleSim to perform functional simulation is definitely the first step. After the functional verification is correct, program the code into the board to view the running results. At this time, we need to use the SignalTap tool. This tool is located in Tools->SignalTap II Logic Analyzer.
The operation process is simple as follows:
1. Complete a single compilation of the project;
2. Open the signaltap graphical interface, add signals, and make related settings; then save it as a .stp file and add it to the project.
3. Recompile and download to FPGA;
4. Open the previous stp file, connect to jtag to trigger, and observe the signal.
Open the SignalTap software, you can see that it is roughly divided into the following parts.
This part is the JTAG Chain, used to display the connection of JTAG, the name of the FPGA chip and the download of the sof file.
This part is used to display the current status and resource consumption information.
This part is used to display configuration information. Sample depth is the number of data collected. The more the collected data, the more RAM is needed, and the RAM type is the type of RAM used. Because SignalTap needs to take up resources, improper settings may cause the wiring on the board to not fit.
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clock: Sampling clock, select the clock in the design or input from outside. Each rising edge of the data is sampled and stored in RAM. The higher the frequency, the more data is sampled near a point, and the more fidelity the signal; Sample depth: the sampling depth is the storage allocated to the sampled data The size of the space. These two parameters determine a problem. The Sample depth is fixed, and the higher the sampling frequency, the sampling time span is very small near the trigger point, and only the signal changes within a short time range of the trigger point can be sampled. Therefore, these two parameters are carefully selected.
segmented: This setting allows us to segment the buffer, which means that we can view multiple trigger points at the same time. For example, the sampling depth of 128kb can be divided into two buffers of 64k x 2. In the same display interval, you can view two consecutive The trigger result of the trigger point.
storage qualifier: This setting helps to specify the type of data stored in memory during debugging. In the default mode, this option of signalTap II is "continuously", which means that each one is captured and stored continuously Clock edge data, in addition, in this mode, you can specify to capture and store certain signals in the design. Other options are as follows:
Input Port: When the input signal is high, capture data. In this mode, a port will be generated, and we need to give it a signal
Transitional: Capture and store data when the specified data changes.
Conditional: Allows to set a storage enable signal as a storage condition, and this signal is also used as a trigger input signal.
That is to say, when the trigger condition occurs, those signals will be stored in the ram. These settings are used to determine, usually directly select continuously
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One very important place here is Trigger, which is to set the trigger state. For example, you want to monitor the output of a certain FIFO. If you do not set the trigger, then you can only see one value output of the FIFO at a time, not a series of values. Output. The Node here is the set trigger signal, and the Pattern below is the trigger condition. The trigger condition here is that the da_ren signal is set high. Of course, you can also select a signal to capture the signal on the rising or falling edge.
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Let's take a look at the setting of trigger conditions:
trigger flow: Trigger flow, which is the sequence control of triggers. The optional parameters are: sequential and state-based;
Sequential: Before triggering the acquisition buffer, calculate all trigger conditions sequentially, that is, when one trigger condition is met, determine whether the second trigger condition is met, and so on, trigger when all are met.
state-based: In this mode, you can customize the trigger sequence. When you debug your design, you have further control over the trigger conditions. You can view the trigger conditions in each state and edit them in the "state-based trigger flow" state machine editor.
triggle position: set the sampling position, there are three sampling positions available
Pre-trigger position: Save the signal status information after the trigger signal occurs (88% data after trigger, 12% data before trigger).
Center-trigger position: Save 50% of the data before and after the trigger signal occurs.
post-trigger position: save the signal status information before the trigger signal occurs (88% data before trigger, 12% data before trigger).
I didn’t understand the above setting at the time. I always thought that when the trigger signal occurred, the sampling clock began to sample the data after the trigger point until the RAM of the sample storage was slow; in fact, it is not, the sampled data is placed in In a cyclic acquisition buffer (the size of the sample depth setting), the sampling clock is always sampling the observed signal, and this buffer always replaces the later old data with the latest data. When the trigger condition occurs, signaltap continues to collect the data after the trigger condition occurs, so as to be the data after the trigger. The above three settings are to set how many points before the trigger condition occurs after the trigger is set, and how many points need to be collected. For understanding, please refer to the figure below:
trigger conditions: trigger levels
The multi-level trigger function provides more precise trigger conditions. In multi-level triggering, SignalTap Ⅱ first judges the trigger expression of the first level, when the result is TRUE, then judges the trigger expression of the second level until all the trigger conditions are met, SignalTap Ⅱ starts to capture the signal .
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Here is the place to select the signal. What signal you want to select, you need to add it here.
Let's talk about the specific usage method.
First, you need to compile the project, then enter this interface, and select the reference clock at the Clock of Signal Configuration.
The Options column is hidden by default. Click the position of the red box in the figure to display it. I don’t know the difference between the several options in Filter. The default value is SignalTap II: post-fitting, but in this case, some signals will not be found, and there is ~ after the signal. I don’t know what exactly meaning. If you want to view all the signals, choose SignalTap II: pre-synthesis. I don’t know what effect this option will have on the results. I will update it on the blog when I learn about it later. Look in is to narrow the scope. If it is a large project, you will get too many signals by directly clicking on the List. It will be more troublesome to find the desired signal. Include subentities means whether to include sub-modules, and Hierarchy view means whether Display in tree shape. Generally, we will check both.
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A. There are two ways to compile the project, one is full compilation (start compilation), the other is just compilation (start analysis & synthesis), without mapping (mapping), these two methods will correspond to two The network node (node) is our signal name. The increase of signaltap observation points is to use these nodes as user interaction information. After "full compilation", according to the fully compiled netlist, the corresponding node information selects signaltap II: post- fitting; After "start analysis & synthesis" is compiled, signaltap chooses signaltap II: pre-synthesis; then what is the difference between the two?
Select pre-synthesis: use the node information in the synthesized netlist of "start analysis & synthesis" as the signaltap information node, and add it to the project, compile the project again, it will re-synthesize and re-layout the entire project All logic.
Choose post-fitting: The use scenario of this node is given in the official document. It probably means that when our project is compiled and downloaded to the FPGA, it is found that there is a problem with the project. At this time, I want to add signaltap to analyze the problem, but I don’t want to Change the result of the previous placement and routing. At this time, select this node as the source of observation information, and quartus will automatically start incremental compilation to compile the added signaltap logic, and retain the previous logic routing and layout results.
According to my understanding, signaltap uses pre-synthesis for "premeditated" cases, and post-fitting for "unexpected" cases.
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In the Data section of the Signal Configuration, select Sample depth and RAM, this will just follow the default values If the remaining RAM is still a lot, you can sample more.
This is an icon of adding a signal. The Trigger Conditions behind it means that when a certain condition is met, data is collected, otherwise it is not collected. After finishing these settings, click Save all on the QuartusII interface, and then recompile.
After connecting the board, you will see the following picture, which shows the current chip name.
After the compilation is complete, download it. If you want to download a .sof file, then download the file at the SOF Manager in the above figure. If you download a .jic file, then download it in the Programmer. The truth is the same.
Click the continuous running button, which is the position of the red box in the above figure, and you can see the interface as shown in the above figure.
You can click File->Export to export the data for further analysis. There are many formats of exported data, such as .csv and .bmp. Of course, it can also be used to analyze data by stopping the operation.
1. Precautions for use
a) The logic analyzer needs hardware support, so not all FPGA chips support it.
b) The general process is: complete the design-compile the project-create a SignalTapII (.stp) file and add the project-recompile-download the design to FPGA-display the waveform of the signal under test in the Quartus II software; After completion, delete the logic analyzer from the project.
c) The sampling clock determines the resolution of the displayed signal waveform. This clock should be greater than the highest frequency of the signal under test.
d) Some signals of the logic analyzer cannot be measured, as follows: the carry signal of the logic unit (carry chain)/clock output of the PLL/JTAG pin signal/LVDS signal
2. Adding signalTap II to the design, causing problems and solutions
FPGA resources are limited. The design has taken up considerable resources (% LE,% MB), and signaltap has to grab resources with the design. "Preemption" is very appropriate here, including preemption of LE and MB, as well as layout resources and wiring resources. I call the impact of "preemption" the "uncertainty principle". This principle is a basic principle throughout the debugging of signaltap. In a word, it is "the observation of the signal will influence the signal". Most of these influences cannot be expressed, or they are not deliberately observed; however, the effect that appears is that the original design function has changed. Some changes are that the original bug does not appear (this should be regarded as a bad change), and some changes are that a new bug has appeared.
According to my analysis, the possible reasons for these effects are as follows:
1) The signaltap tool itself has bugs. I can't confirm this, I just guess. The principle of signaltap is to insert trigger logic and storage logic and a virtual JTAG link for communication with a PC in the designed netlist to realize the function of an embedded logic analyzer. This insertion process is completed by QUARTUS software and is invisible to the user. Since users cannot control and constrain this process, it is possible that the circuit function after adding signaltap goes against the original intention of the user.
2) The fan-out of the observed signal becomes larger, causing the design timing margin to change. The realization of trigger logic requires the addition of triggers and combinational logic to the signal path, which will inevitably cause the fan-out of the observed signal to become larger and the signal output delay to increase. If the timing of the observed signal is tight, increasing the delay of the signal may make the timing relationship better (the original bug does not appear), or it may deteriorate its timing (bugs appear frequently or new bugs appear) .
3) Due to the existence of "preemption", the timing margin of the design changes. Due to the addition of trigger logic and storage logic, FPGA resources have to be reallocated. The layout position and routing resources of the original design in the FPGA will change, and the timing will also be affected. Often after adding signaltap, the timing analysis results after placement and routing will be worse than the original.
The method to solve the above contradiction is to add as few observed signals as possible. The commonly used methods are:
1) Before each recompilation, make an assessment of the retention of the signal. If the observed signal proves to be irrelevant to the problem to be found, delete the signal.
2) After each successful compilation, check the compilation report. If the logic resource utilization ratio of the system is more than 95%, consider removing some observed signals or removing several trigger levels, or reducing the sampling depth.
3) If necessary, turning off the sampling enable of the signal that only needs to be the trigger condition can also significantly reduce the occupation of logic resources.
4) The occupancy ratio of system storage resources should also be taken into consideration, and not too much. The options related to this are the sampling depth, the number of signals, and whether the signal sampling enable is closed.
5) After the compilation is successful, check the timing analysis report. If the system timing drops significantly or the timing of the observed signal cannot be satisfied, consider using the above method to reduce the occupation of logic resources.
In addition, the selection of the sampling clock has a great impact on the overall timing of the system. The selection principle is:
1) Try to select the signal as the sampling clock from the top level of the design as much as possible, instead of randomly using the input clock of which module as the sampling clock, so that QUARTUS can optimize the utilization of global clock resources.
2) Under the premise of ensuring the observation accuracy, choose a lower frequency clock.
The sampling clock is essentially one of the trigger conditions (the most basic trigger condition). If a non-clock signal (a signal with no certain frequency) is appropriately selected as the sampling clock, it can get twice the result with half the effort.