Table of contents
foreword
This blog is mainly based on the Quartus software to complete the design of a 1-bit full adder, using two design methods: 1) schematic diagram input and 2) Verilog programming. The development board is based on Intel DE2-115.
First, understand the full adder
1. Half adder
1. Definition:
A half adder is a combinational circuit that can add two one-bit binary numbers to obtain a half-add sum and a half-add carry.
2. Truth table:
A and B represent binary numbers, C represents half plus carry, S represents half plus and
2. 1-bit full adder
1. Truth table:
Ain represents the summand, Bin represents the addend, Cin represents the low carry, Cout represents the high carry, Sum represents the basic sum
2. Realize 1-bit full adder through schematic diagram
1. Create a project
Start the Quartus II software, select File->New Project Wizard, click Next in the interface that appears, fill in the path and name of the project, and then click Next until the following interface appears and perform corresponding operations. Then all the way to Next, until Finish, to complete the creation of the project.
2. Schematic design of half adder
1. Design schematic diagram
First select File->New, select Block Diagram/Schematic File to select components after entering
, and add and2 and xor respectively.
Add input and output to complete the design schematic diagram
Save the file and compile
View the circuit diagram through tool->Netlist Viewers->RTL Viewer
2. Simulation implementation
Create a vector waveform file, select the menu item File→New->VWF
to add a signal
, edit the signal
, save the file and start the simulation:
Functional simulation results
Timing simulation results
Through the simulation results, it can be found that the obtained results are consistent with the truth table.
3. Schematic design of full adder
1. Set the design item as a callable component
In the case of opening the schematic file half_adder.bdf of the half adder, select the Create/Update→CreateSymbolFilesforCurrentFile item in File in the menu, and the current file h_adder.bdf can be saved as a component symbol for high-level design transfer
2. Schematic drawing
First select File->New, select Block Diagram/Schematic File after entering,
and then select components:
add adder and or2
to add input and output to complete the effect
Save the file and compile
View the circuit diagram through tool->Netlist Viewers->RTL Viewer
3. Simulation implementation
Create a vector waveform file, select the menu item File→New->VWF
to add a signal
, edit the signal
, save the file and start the simulation
Functional simulation results
Timing simulation results
Through the simulation results, it can be found that the obtained results are consistent with the truth table.
3. Realize 1-bit full adder through Verilog programming
1. Create a Verilog file
2. Code implementation
module full_adder(
//输入信号，ain表示被加数，bin表示加数，cin表示低位向高位的进位
input ain,bin,cin,
//输出信号,cout表示向高位的进位，sum表示本位的相加和
output reg cout,sum
);
reg s1,s2,s3;
always @(ain or bin or cin) begin
sum=(ain^bin)^cin;//本位和输出表达式
s1=ain&cin;
s2=bin&cin;
s3=ain&bin;
cout=(s1|s2)|s3;//高位进位输出表达式
end
endmodule
Save and compile the file
View the circuit diagram through tool->Netlist Viewers->RTL Viewer
3. Simulation implementation
Create a vector waveform file, select the menu item File→New->VWF
to add a signal
, edit the signal
, save the file and start the simulation
Functional simulation results
Timing simulation results
Through the simulation results, it can be found that the obtained results are consistent with the truth table.
4. Realize four-bit full adder through Verilog programming
Since we have realized the completion of the 1-bit full adder, a multi-bit full adder can be realized according to the cascade of multiple 1-bit full adders.
So we can also use Verilog programming to realize 4-bit full adder.
1. Code implementation
module adder4 (cout,sum,ina,inb,cin);
input [3:0] ina,inb;
input cin;
output [3:0] sum;
output cout;
assign {
cout,sum} = ina + inb + cin;
endmodule
Save and compile the file
View the circuit diagram through tool->Netlist Viewers->RTL Viewer
2. Simulation implementation
Create a vector waveform file, select the menu item File→New->VWF
to add a signal, the steps are the same as above
Edit signal
Functional simulation
Timing simulation
V. Summary
This study is mainly an introduction to FPGA programming, and I learned the basic principles and theories of the full adder. And based on the Quartus software, we use schematic design and Verilog programming to design the most basic 1-bit full adder. On this basis, we can design multiple 1-bit full adders according to the cascade of multiple 1-bit full adders. Although we can have a deeper understanding of its principle through this method, this method of using schematic design is very cumbersome in testing with many components, so I suggest using Verilog programming to implement multi-bit full adders.