One full adder and four full adders——FPGA

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foreword

Environment:
1. Quartus18.0
2. vscode
3. Development board based on Intel DE2-115

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1. One-bit full adder

• Introduction to the full adder:
  the English name of the full adder is full-adder. It is a combination circuit that uses a gate circuit to add two binary numbers and calculate the sum. It is called a full adder. A full adder can handle the low-order carry and output the carry of the addition of this bit. A multi-bit full adder can be obtained by cascading multiple one-bit full adders. Commonly used binary four-bit full adder 74LS283.

• Input and output truth table:

The truth table of a full adder is shown in the figure below, where Ai is the addend, Bi is the addend, the carry from the adjacent low bit is Ci-1, and the output sum is Si. The number of carry to the adjacent high bit is Ci

1. Schematic design of a full adder

The project creation process will not be repeated here. It has been introduced in detail before, and the chip model can be selected as EP4CE115F29. See below for specific operations:
https://blog.csdn.net/qq_52215423/article/details/127832959

• Before implementing a full adder, you need to design a half adder:
  click File->new:
  
• Select components:
  
  -Add input and output channels to complete the design:
  
• Effect:
  
• View the RTL diagram:
  
• Set the designed half adder as a callable element:
  

Save it as half_adder, the blogger here named the half adder as quanjiaqi
, and the full adder as quanjiaqi1.

• Schematic for designing a full adder:

• create a new file:
  

• Add components:

• Effect:
  
• RTL diagram:
  

2. Verilog programming of a full adder

• 1. Create a Verilog file:
  
• code:

module shiyan1(
	//输入信号，ain表示被加数，bin表示加数，cin表示低位向高位的进位
	input ain,bin,cin,
	//输出信号,cout表示向高位的进位，sum表示本位的相加和
	output reg cout,sum

);
reg s1,s2,s3;
always @(ain or bin or cin) begin
	sum=(ain^bin)^cin;//本位和输出表达式
	s1=ain&cin;
	s2=bin&cin;
	s3=ain&bin;
	cout=(s1|s2)|s3;//高位进位输出表达式
end
endmodule

• RTL circuit diagram:
  

3. The board effect

one bit full adder

Two, four-bit full adder

1. Schematic design of four-bit full adder

• Set a one-bit full adder as a callable element:

• Schematic:

• RTL circuit diagram:

• simulation:

2. Verilog programming of four-bit full adder

• Create a file:
  
• code:

module full_adder4(
    input[3:0] a,b,
    input cin,
    output[3:0] sum,
    output cout
);
    assign{
    
    cout,sum} = a+b+cin;
endmodule

• RTL circuit diagram:

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3. Summary

Since the operation of the four-bit adder was not completed in the experimental class, there is no effect video on the board here. This experiment is mainly to use the full adder to get started with FPGA knowledge. By designing the schematic diagram by yourself, you can know the internal wiring of the project more clearly, with greater freedom and more intuitive. However, through verilog programming, RTL circuit diagrams can be realized by programming without knowing what is inside, and the project will generate relatively better RTL circuit diagrams according to the resources and circuits used.

4. References

1. FPGA—the realization of 1-bit full adder
2. Programming Verilog four-bit full adder