Table of contents
Preface
When using experimental courses in EDA courses, you need to do Gray code simulation experiments, so make a process and avoid some mistakes.
Friendly reminder : If after using the cracker, you find that the code fails to run and the error shown below appears, check your computer system. If it is a win11 system, it is recommended to delete the cracker (license.dat file) and use the 30-day free use permission directly.
Operating procedures
1. Create project engineering
(1) Open the quartus software, 32-bit is recommended. If it is 64-bit, the process can be the same. Since my system is inconsistent with the software, I will use it for 30 days and create a new project.
(2) 1. File storage directory (Create a folder Greyy on the desktop in advance and place it in the specified folder)
2. File name, exp2 ( needs to be consistent with the name in the code, otherwise an error will be reported )
3.Next step
(3) Import the code file. If there is one in advance, just import it directly. If not, you can also create a new VHDL file after the creation is completed and write the code. Here I will import it directly. If it is not imported, just go to the next step. I will give it later. Create new method
After importing, be sure to add it, and then proceed to the next step.
(4) Select the chip type, EP2C5Q208c8, just select according to the red line, then next; keep next until the end
(5) Run the code program
run successfully
(6) If there is no import in the third step, you can create a new file>>new>>vhdl file, click OK, and add the code
code
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------
entity exp2 is
port( K1,K2,K3,K4,K5,K6,K7,K8 : in std_logic; --输入:8位格雷码
D1,D2,D3,D4,D5,D6,D7,D8 : out std_logic --转换结果
);
end exp2;
--------------------------------------------------------------------
architecture behave of exp2 is
begin
process(K1,K2,K3,K4,K5,K6,K7,K8) --格雷码转换
begin
D1<=K1;
D2<=K1 xor K2;
D3<=K2 xor K3;
D4<=K3 xor K4;
D5<=K4 xor K5;
D6<=K5 xor K6;
D7<=K6 xor K7;
D8<=K7 xor K8;
end process;
end behave;
2. Edit chip pins
1. In the toolbar above, select pins in Assignment to open;
2. Edit the pins, click the location below, and set the configuration for the input and output pins respectively. Only set the location. After completion, you can close it and save it automatically. It is recommended to use the import function in the third step, provided that you have done it. pin file
3. Use the imported pin configuration information. The function is the same as the previous step. If you have already selected one by one, ignore this step.
.qsf file, which is the pin configuration information
4. The pin configuration success page, so that you can
3. Configure simulation files
(1) Create a new VWF simulation file, file>>new>>Vector Wavefrom File file, OK
(2) Import the chip pin information and operate according to the picture below
Just click OK, no need to change other
Successful screenshot
When the above appears, the simulation file is ok;
(3) Draw input waveform diagram
First select the lifting position of the input end, then select lifting, and draw more
(4) Click Run and find an error because it is not saved and used in the simulation tool.
(3) Save the simulation file, otherwise an error will be reported when running. It is recommended to save it in the Grary folder.
(4). Select the vmf file in the save location in the simulation tool, so that it will be used during operation.
processing>>simulator tool
There is no need to save the following, just close it after configuring it.
(5) Click Run Success again and the simulation is successful.
All operations are over! ! ! success
Follow and like to avoid getting lost! ! !
Follow and like to avoid getting lost! ! !
Follow and like to avoid getting lost! ! !