table of Contents
Grammar knowledge point 1: Verilog HDL models of different abstract levels
1. Verilog HDL has the function of behavior description and structure description
2. Digital circuit system design (take sine signal generator as an example)
Grammar knowledge point 2: assign continuous assignment statement (data flow description method)
Experimental task three: hardware verification of the function of the frequency meter.
Experiment summary and analysis
Purpose
Design an 8-digit hexadecimal frequency meter and learn more complicated digital system design methods.
Experiment preview
Review the design of counters and registers.
Principle of the experiment
(1) What is the function of the frequency meter? (Instrument for measuring frequency)
(2) What does the attributive "8-digit hexadecimal" in front of the frequency meter limit? (Frequency measurement range of the frequency meter)
According to the definition of frequency and the basic principle of frequency measurement, the frequency of the measurement signal must have an input signal with a pulse width of 1 second as a signal allowed for pulse counting. After the 1 second count is over, the count value will be locked into the latch, and the counter will be cleared to prepare for the next frequency measurement count cycle.
Design requirements
Figure 1 shows the schematic diagram of an 8-digit hexadecimal frequency counter.
Among them, the counting enable signal cnt_en of the controller control generates a periodic signal with a pulse width of 1 second, and synchronously controls the en enable end of the 32-bit binary counter cnt32 in the frequency counter. When en is high level, counting is allowed; when low level, it stops counting and keeps the counted number of pulses. During the stop counting period, a rising edge of the latch signal load is first required to latch the count value of the counter in the previous 1 second into the latch reg32 and decode it by the external hexadecimal seven-segment decoder To display the count value. The advantage of setting the latch is that the data display is stable and will not flicker constantly due to the periodic clearing signal. After the signal is latched, there must be a clear signal rst_cnt to clear the counter to prepare for the counting operation in the next second.
This design requires a 32-bit counter. The counter has a 1-second count enable signal and a clear signal. The clear signal is generated in a certain period of time between the two count enable signals. A 32-bit latch is needed. After the count is over, the count value is immediately latched. A control circuit is needed to generate the count enable signal, clear signal and latch latch signal of the counter. The connection relationship between the three modules is shown in Figure 1.
Experiment task one
According to the waveform shown in Figure 2, design the control module of the frequency counter, and describe in detail the function of each sentence in the design, design principle and logic function.
The reference code of the controller :
module control(clk1HZ,cnt_en,rst_cnt,load);
input clk1HZ;
output cnt_en,rst_cnt,load;
reg divclk;
always@(posedge clk1HZ)
divclk<=~divclk;
assign cnt_en=divclk;
assign load=~divclk;
assign rst_cnt=~clk1HZ & ~divclk;
endmoduleGrammar knowledge point 1: Verilog HDL models of different abstract levels
1. Verilog HDL has the function of behavior description and structure description
Behavior description is the description of the logic function of the design circuit, and does not care about the elements used in the design circuit and the connection relationship between these elements. Behavior description is a high-level description method. In Verilog HDL, behavior description includes three abstract levels: System Level, Algorithm Level, and Register Transfer Level (RTL). Should focus on the behavior description method.
Structure description is to describe the structure of the design circuit, that is, describe the components used in the design circuit and the connection relationship between these components. Structure description is a low-level description method. In Verilog HDL, structure description includes two abstract levels: Gate Level and Switch Level.
For an actual digital system circuit, the behavior description method is generally used to design the bottom module circuit, and finally the structure description method is used to connect the modules to form the top file to complete the design of the system circuit.
2. Digital circuit system design (take sine signal generator as an example)
Method 1: Use the schematic diagram method to realize the digital circuit system design, as shown in the figure.
Example: The figure shows the digital system design of a sine signal generator.
Method 2: Use module instantiation sentences to realize digital circuit system design.
Module instantiation statement format:
Design module name <instantiation circuit name> (port list);
Example circuit name: The identifier defined by the user for the system design, which corresponds to the
list of socket ports where the design module components are inserted on the system circuit board : the table of pin names on the socket corresponds to the I/O port of the design module.
The following source code is the digital system design of the sine signal generator.
Grammar knowledge point 2: assign continuous assignment statement (data flow description method)
The assign continuous assignment statement describes the logical relationship between input and output, and its format is:
assign target variable name = drive expression
The target variable name must be a wire variable; the default input and output port of the synthesizer is a wire variable. If the target variable name requires a variable other than the port, it must be defined in advance with a net-line variable definition statement. The format of the net line variable definition statement is:
wire [width-1 : 0] variable 1 , variable 2…… ;
The assign continuous assignment statement is a parallel statement, which can be transformed into an always@ statement. The execution process is: any signal in the driving expression on the right side of the equation changes, this expression is calculated once, and the obtained data is immediately assigned to the target variable on the left side of the equation.
The same target variable is not allowed to have multiple different assignment expressions, or wire type variables are not allowed to have multiple drive sources. E.g:
assign dout=a&b|c;
assign dout=e&f|d;
The above expression is wrong.
The assign statement is mainly used to describe a combination circuit, but if the signal has feedback, it will also form a sequential circuit.
Experimental task two
Complete the complete design of the frequency counter, and give its frequency measurement timing waveform and its analysis.
Reference code for 32-bit binary counter:
module cnt32(clk,en,rst,q);
input clk,en,rst;
output reg[31:0] q;
always@(posedge clk or posedge rst)
begin
if(rst) q<=0;
else if(en) q<=q+1;
end
endmoduleReference code for 32-bit latch:
module reg32(D,Q,load);
input[31:0] D;
input load;
output reg[31:0] Q;
always@(posedge load)
Q<=D;
endmoduleThe overall design of the 8-digit hexadecimal frequency counter is shown in the figure, and the simulation waveform is shown in figure 5:
Note: The design includes 4 files, namely the bottom design controller control.v, counter cnt32.v, latch reg32.v and top design frequency.bdf. Make sure that these four files are in the same folder. , And the folder is not nested.
Experimental task three: hardware verification of the function of the frequency meter.
Experimental proposed election circuit pattern 5 test certificate frequency meter function, wherein eight digital display in hexadecimal frequency measurement output ; measured by the frequency input FIN clock0 input , frequency selective 4Hz, 256Hz, 3MHz ‥‥‥ 50MHz Etc .; 1Hz frequency measurement control signal CLK1Hz can be input by clock2 (select 1Hz with jumper). Perform hardware test after compiling and downloading.
Experiment summary and analysis