Was added signal Quartus SignalTap tool found signal is added to red, as shown data_slave [7..0] :
Such a signal is no way observed, will not be updated in accordance with the SignalTap Clock and Trigger, because it will be omitted Synthesis process,
Adding comprehensive option (Synthesis Attribute) allows the synthesizer to keep these signals do not contribute to the top-level input and output modules, commonly used are:
wire[7:0] cnt/*synthesis keep*/; // Keep the Entity of Wire
reg signed[11:0] corr_i_out/*synthesis preserve*/; // Keep the Entity of Register
Indeed, the output can be used Keep combinational logic, sequential logic and the output signal of the common block preserve option.
At the same time, the red invalid SignalTap signals may affect other signals SignalTap in. Such a blank check into the SignalTap among the components, a great probability will affect the timing of the system, such as that of all other signals to be observed not observed it!
In the design and debugging time must cancel such a "blank check."