When FPGA debugging, we will be in addition to the simulation often used SignalTap board-level debugging, it can change real and effective reaction of certain variables, to help us understand the inner jump, convenient Debug operation. SignalTap need to develop the clock, selected according to demand, due to the sampling Nyquist sampling theorem follows.
Sometimes we often encounter such a situation in the Debug, and can not be observed in the values of all variables in the SignalTap. Some variables will be added into the red panel, which means SignalTap fetch less than this value. The reason for this is that, when integrated in the synthesis of some of the variables are optimized, so it does not show up. Hereinafter, for both types of variables, wire and reg, respectively on how to let the normal display. Knowledge of this part is actually very simple, basic idea is to use an integrated property Synthesis Attribute to control some optimization during synthesis.
wire-type variable
This one can also view concerning integrated property variables in the language template in Quartus. Integrated wire variable properties in the 13 template Quartus shown below, the main command keep command. Quartus software gives the relevant introduction.
// Prevents Quartus II from minimizing or removing a particular
// signal net during combinational logic optimization. Apply
// the attribute to a net or variable declaration.
(* keep *) wire <net_name>;
(* keep *) reg <variable_name>;The main wire is to prevent the relevant variables is optimized in an integrated or omitted.
Summed up the wire-type variable comprehensive property configuration following two methods.
1. (* keep * ) wire <net_name>;
2. wire <net_name>/* synthesis keep */;Wherein a first written to verilog-2001 standard, the second standard as before, both compatible. Note that when using the wording of the second, the comments section must be written before the semicolon.
reg variables
Reg comprehensive attribute variables in the 13 template Quartus shown below, the main command and preserve noprune command.
// Prevents Quartus II from optimizing away a register. Apply
// the attribute to the variable declaration for an object that infers
// a register.
(* preserve *) <variable_declaration>;
(* preserve *) module <module_name>(...);Reg optimized away preventing a certain type of part or in whole, may be used for a particular variable reg can be used for all of the variables in a module.
// Prevents Quartus II from removing or optimizing a fanout free register.
// Apply the attribute to the variable declaration for an object that infers
// a register.
(* noprune *) <variable_declaration>;Prevent a variable optimized away reg no fan-out, there may be unrelated to the amount, there may be an intermediate amount.
Summed up a reg variable comprehensive configuration attributes are the following.
1. (* noprune *) reg <variable>;
2. (* preserve *) reg <variable>;
3. (* preserve *) module <module_name>(...);
4. reg <variable>/* synthesis noprune */;
5. reg <variable>/* synthesis preserve */;
6. module <module_name>(...)/* synthesis preserve */;Also there are two ways for writing, are two standards, any reader can choose a find convenient. Also note that the location of a semicolon, it is more important to say one more times. There are two type reg, usually choose, if not on for another try, there will always be a form of ok.
to sum up
With such adjustable integrated property, you can add any of the intermediate variables during board-level debugging to observe operating conditions, to facilitate the Debug great extent, improve efficiency.