The complete servo system contains many modules, so it cannot be introduced in detail one by one, so this chapter focuses on introducing
Design the more difficult
FPGA
part and briefly introduce
the workflow of
the ARM side.
The FPGA part mainly includes FOC
Algorithm, current sampling algorithm and encoder sampling algorithm are the basis of the whole control system and directly determine the motor control
The effect is good or bad. Due to the particularity of
the FPGA
work, it is necessary to consider the rationality of the design timing and rationally coordinate various
The execution order of the tasks has greatly increased the difficulty of its design. The following will
set up the important part of
the FPGA program
According to the design description, it is mainly divided into
SVPWM
algorithm module, encoder feedback module and current sampling module.
4.1 SVPWM
algorithm programming
According to the fourth section of Chapter 2,
the workflow of the
SVPWM algorithm is shown in Figure
4-1 . First of all the input
Decoding
and judging the current sector, and then calculating the action time required for the basic vector of the current sector, the next step
is
At the time point of PWM
comparison value, finally perform pulse width modulation and add dead time to form complementary
PWM
wave drive control inverter
The switch works so that it generates the required sinusoidal voltage.
4.1.1
Software module design
The functional structure diagram of the
SVPWM module is shown in Figure
4-2
. The signals of the module are interpreted as follows:
（
1
）
sys_clk
: System clock, operating frequency is
50MHz
.
（2）
sys_rst
: System reset, active low.
（3）
svpwm_en
: Module enable signal.
(4)
ualpha
,
ubeta
: the output signal of the inverse
Park
conversion module.
(5) Others
: Six complementary
PWM
waves.
The working principle and calculation formula of this module have been elaborated in Chapter 2, so I won’t go into details here.
However, it should be noted that due to the mechanical delay of the switching of the inverter, it is necessary to generate a complementary
PWM
wave, which can avoid short circuit and injury caused by opening the upper and lower bridge arms at the same time.
The principle of generating complementary PWM wave
with dead zone
is to use the calculated
PWM
wave as a reference object, and then according to
The actual situation sets a reasonable dead time. Assuming that the inverter input signal is active high, when the reference object changes from low
When the level jumps to a high level, first close the lower bridge arm, then delay the dead time, and finally open the upper bridge arm; when referring to
When the object jumps from a high level to a low level, first close the upper bridge arm, then delay the dead time, and finally open the lower bridge arm.
The effect is shown in Figure
4-3
. Taking
the U
phase as an example,
u_pwm in the figure
is the calculated reference
PWM
wave,
u_pwm1
is the PWM wave
of the upper bridge arm
, and
u_pwm2
is the PWM wave of the lower bridge arm.
4.1.2
Simulation test
Perform simulation verification on the
SVPWM module, and the results are shown in Figure
4-4 . It can be seen from the figure that any
The value is assigned to
u_alpha
and
u_beta
, and then the system generates a clock cycle
svpwm_en
signal, after operation
Get
u_pwm
as the reference
PWM
wave.
Generate complementary PWM waves u_pwm1 and u_pwm2 according to
the u_pwm signal
,
There is a dead time between the two. It can be seen from the simulation results that the module can normally generate complementary PWM waves.
4.2 BISS-C
protocol program design
4.2.1 BISS-C
protocol data structure
The BISS
protocol comes from
iC-Haus
company, it is suitable for the bidirectional serial interface of the sensor, and it has
CRC
calibration
The verification function ensures that the transmitted data is correct. Compared with other similar communication protocols,
the BISS
protocol has advantages in compatibility and network structure
It has more advantages in terms of high speed and delay than
SSI
, and the communication rate can reach up to
10Mbps
. At the same time,
BISS
The data length of the protocol can be modified according to the actual situation, and has good scalability.
The BISS
protocol has two working modes
[43]
. The working mode designed in this paper is the sensor mode, and
the
FPGA
The encoder sends a position request command, and the encoder returns relevant information. In sensor mode,
BISS-C
data
The format is shown in Figure
4-5 below
. The host sends
the MA
clock signal to the grating scale, and the encoder serializes through
the SLO
data line
Return data information.
The BISS-C data frame consists of eight parts, which are the "Ack" response phase, the "Start" bit, the "0" bit of a bit,
Several bits of position data, one error bit, one warning bit, six
CRC
check codes and
"Timeout"
timeout result
end stage. The specific communication request cycle is as follows
[44]
:
(
1 ) When it is not a position request, the clock signal is at high level, and
the SLO data line
of the host reading the encoder
is at high level
Normally, it means the encoder is ready.
（
2
) When the encoder is ready, the host starts to transmit the fixed-frequency
MA
clock signal to the grating scale.
（
3
) The encoder will set
the SLO line low when it detects the second rising edge of the
MA clock sent by the master
level as a response.
（
4
) The encoder prompts the host by pulling down
the SLO
signal line, the current encoder is in
the Ack
response state, the host
The machine should switch to the receiving state in time.
（
5
) The host will synchronize with
the MA
clock signal to receive the encoder and send back the data, and the data frame format is high bit in
The front low is behind.
（
6
) After receiving all the data, the host pulls
the MA
clock line high. When the encoder is ready for the next position
When requested, the encoder sets
the SLO
line to a high level to prompt the host, otherwise it remains low.
4.2.2
Software module design
The functional structure diagram of
the BISS module is shown in Figure
4-6
, which is mainly composed of
the MA
module,
SLO
module and
CRC
module.
The signals of the module are interpreted as follows:
（
1
）
biss_en
: Module enable signal, used to obtain encoder position information.
（2）
data_length
: Encoder data bit width setting.
（3）
SLO
:
BISS
protocol data line.
（4）
MA
:
BISS
protocol clock line.
（5）
abs_data
: Single-turn absolute value, used for multi-turn counting and electrical angle calculation of circular encoders.
（6）
abs_pos
: The actual total position data of the encoder.
The specific working principle of this module is as follows: first,
the FPGA
sets the position data bit width according to the actual grating scale model
data_lentgh
value, this module meets the design requirement that the position data bit width length is within
32bit
. Through the main control module
Send the enable signal
biss_en
to
the MA
module,
the MA
clock module starts to work, and sends a fixed frequency to the grating ruler
The
MA
clock signal requests to get the current position value.
After the FPGA
receives the data returned by the grating scale, it will input
Go to the
CRC
verification module for data verification, and finally output the correct position data to the next-level module.
According to the characteristics of the timing diagram of
the BISS
protocol, this paper divides the process of receiving data by the
SLO
module into six states,
The state machine works as shown in Figure
4-7
. At the beginning, the function module is in the idle state and enters the waiting state; when
When the grating ruler pulls down
the SLO
signal line, it enters
the Ack
response state; when
the SLO
changes from low level to high level, the state
The state machine enters
the STATE_ZERO
state; when it is detected that
the SLO
data line is pulled low, the module enters the working state and starts
Receive data, and enter the "TIMEOUT" state after receiving the set bit width data.
In actual engineering, there are glitches or metastable phenomena in the data level, if according to
the rising edge of
the MA clock
The signal obtained by reading the level state of the current SLO data line is not reliable.
Usually, during transmission
The level state in the middle of the data is relatively stable and reliable. Therefore, the method adopted in this paper is: in the middle part
Sampling
the SLO
data line multiple times, and judging which level has the largest number, and finally the level signal value with the largest number
Judgment assigned to the register. The specific implementation principle is shown in Figure
4-8
, where
sys_clk
is the system clock and
bps_cnt
is a
The number of samples of the SLO data line level in one
MA
clock cycle .
The actual MA clock frequency is compared to the FPGA internal
The operating frequency is a low-speed clock, so multiple sampling can be performed in one
MA
clock cycle. in every
During
MA clock cycles, when the rising edge of
the MA clock
is detected
,
The bps_cnt
register starts counting samples from zero,
Then judge whether the number of high levels is large or the number of low levels is large, and finally the value of the side with the largest number of levels will be accumulated
Assign to a register. Repeat this process to receive all the data.
After the
SLO
module receives the data, it returns a reception completion signal to
the MA
module and the
CRC
check module.
MA
mode
After the block receives the completion signal,
the FPGA
will pull
the MA
clock line high, and
the CRC
module will set the
SLO
mode to
The data frame transmitted by the block is subjected to
CRC
check operation.
The CRC polynomial of
the BISS-C
protocol is
G ( x ) x 6 x 1 ,
That is, the check field is
1000011
. In order to give full play to the working characteristics of
FPGA
parallel processing and further improve work efficiency
rate, this article uses a parallel
CRC
check algorithm to get the
CRC
check code in one clock cycle, the main code
As shown in Figure 4-9:
Among them,
d[33:0]
is the data that needs to be verified, and
crc_out[5:0]
is
the operation of the
CRC module on the data that needs to be verified.
The result obtained after the calculation, and the initial value of
c[5:0]
is zero, and finally the calculation result is compared with the received
CRC
check code
line matches. If the two are consistent, it means that the
SLO
module receives the data correctly and updates the correct position data to
In the next-level module, otherwise update the correct data reserved last time, and prepare to initiate the next raster position request.
4.2.3
Simulation test
Finally, write a test file to
simulate and verify the
BISS
module in
ModelSim software, and apply it in actual engineering
Stability plays an important role.
Therefore, the highest 5Mbps
is selected in terms of communication rate
, so the model in the test file
The virtual encoder transmits data to
the FPGA at a communication rate of
5Mbps
. This article is for commonly used 26bit and 32bit positions
Data bit width encoder models are tested.
First, set two sets of data for
26bit wide models as
shown in Table 4-1, where the first set and the second set of data are only
Only the last bit of the
CRC
check code is different, and the second set of data is completely correct. Through this artificial
The set data can test
whether the two sets of data information received by the
BISS module are consistent, and also detect
the CRC check mode
block to work properly. It should be noted that
the CRC check value of
the BISS-C
protocol
is first
It is output to the host by inverting, so
the CRC
check value in the table has been inverted. so make a match
When matching and checking,
the FPGA
should invert the calculated
CRC
check value and compare it with the received value. the whole
The body test results are shown in Figure 4-10.
The timing diagram on the left side of the figure is the first set of data, while the one on the right is the second set of data. In the figure,
crc_check
is receiving
CRC
value, check_data is the data to be verified, done is the data receiving completion signal, crc_out
is
the verification
The calculated
CRC
value,
crc_done
means that the verification is complete, that is, the received data is correct. It can be seen from the picture
In the data mode where
the data_length
is
26bit
, after the module receives
the biss_en
enable signal,
the FPGA
sends the
The encoder sends an
MA clock signal with a frequency of
5MHz
. The encoder passes the SLO data after detecting the MA clock signal
The line returns data to the host, and when
the
FPGA
finishes receiving the data,
it transmits the received
CRC
check value and
The data needs to be verified, and a
done
signal is sent to prompt the
CRC
module to work. Then the
CRC
module needs to check the
The verified data is processed, and after processing , it is compared with the received
CRC check value, if the two match successfully
Then a successful mark signal
crc_done with a high level pulse is generated
, otherwise the crc_done signal remains low.
Further check
the details of the
CRC check, as shown in Figure
4-11 . The received CRC check value crc_check in the figure
is
001011
, and
the crc_out is 110100 after
the CRC check is performed on the data to be checked
. previous section also
Speaking of, the CRC check value
of the encoder
is first inverted and sent to the host, and the data obtained after the check operation
The crc_check
is not inverted, so it can be seen that it is consistent with the received
CRC
check value after inversion. It can also be seen from the figure
The time required for the
CRC
check is one system clock cycle, so it can be concluded that the CRC check module can work normally.
From the above two simulation result diagrams, it can be seen that
when the
BISS
module can
normally send MA at a communication rate of
5Mbps
The clock signal, and the encoder data is completely received, and finally
the CRC
check operation is completed in one clock cycle. Therefore all
The designed
BISS
module has passed the
26bit
mode function simulation test.
Similarly, the simulation test of the 32bit wide model
is set
, and the simulation data set is shown in Table
4-2
, and the function simulation
Figure 4-12 and 4-13 show the real image and
CRC
check details
. It can be seen from the figure that the designed BISS module is also
Passed the 32bit mode function simulation test.
Therefore, it can be concluded that the BISS module
designed in this paper
can change
the data_lentgh
register to be able to
5Mbps
communication to completely receive
the data of the encoder with a data bit width within
32bit .
4.3
Tamagawa protocol program design
4.3.1
Tamagawa protocol data structure
The Tamagawa agreement comes from Japan's Tamagawa Corporation, and the Tamagawa agreement uses a "one-question-one-answer" communication method
In this way, the host sends different request commands to the encoder to obtain different data information
[45]
. It communicates with the string
The port communication is consistent, and when sending a byte of data , it will be transmitted from the low bit at a fixed transmission rate of
2.5Mbps .
This article only focuses on the working mode of Tamagawa protocol to read encoder information.
The data frame format for reading encoder information mode is
shown in Figure 4-14. Its working principle is: the host sends
Different control frame commands are given to the encoder to obtain corresponding information, and then the encoder returns a set of data as a response,
This group of data consists of control frames, status frames, several data frames and
CRC
frames. Among them, according to the different encoder models,
The number of dataframes will vary.
The data format of the control frame is shown in Figure
4-15
. The frame data subject part consists of synchronization code, control instruction and control
The instruction check digit consists of three parts. Among them, the synchronization code is fixed, while the control command and its check digit have specific
command code, as shown in Table
4-3
. Different instruction codes represent different functions, and the data types returned by the encoder are also
different. For example, if the user wants to obtain the single-turn value and multi-turn value of the encoder, look up Table
4-4
to know that the
instruction numbered
ID 3
The code corresponds to the encoder returning single-turn value and multi-turn value, so the host can send the code to the encoder as:
01011000
,
When the encoder receives the encoded information, it returns the current encoder single-turn value, multi-turn value and other additional information data.
The data format of the status frame is shown in Figure
4-16
, which consists of information bits, coding error alarm bits and communication alarm bits.
Different encoder models correspond to different information bits. For specific meanings, please refer to the corresponding encoder manual.
introduce. If the encoder code is wrong or there is a problem with the external power supply of the encoder, the encoder error alarm bit
ea0
If it is
1
, it means that the current encoding information is wrong, and when
ea1
is
1
, the multi-turn value data of the encoder is wrong. Communication alarm bit
When ca0
is
1
, it means that the check bit of the control command in the received control frame has an error, while
ca1
is
1
, it means that all
An error occurred in the end bit of the received control frame.
The Tamagawa absolute encoder can realize high-resolution position encoding data with a bit width of up to
39 bits
, including
23bit
single-turn value and
16bit
multi-turn value. But Tamagawa protocol communication only sends
8bit
data at a time, so send
To send complete location information, it must be disassembled and then sent in a certain order. A specific byte of data
The frame format and
CRC
frame format are shown in Figure 4-17.
Since the host sends different command codes to the encoder, the data types returned by the encoder are also different. According to encoder
With different resolutions and command codes, the number of effective data frames returned by the encoder is also different. For example, only one-turn value can be obtained
or multi-turn value, return a valid data frame of
3 bytes, and return
8
if you need to obtain both single-turn value and multi-turn value
A valid data frame of bytes. The data frame corresponding to the specific function code is shown in Table 4-4.
In the table,
ABS
represents the single-turn absolute code value,
ABS0
is the lower eight bits of the single-turn position data, and
ABS1
is the single-turn position
The middle eight bits of the data,
ABS2
is the upper eight bits of the single-turn position data, if the number of single-turn code values of the encoder is less than
24bit
, the high bits are filled with
0
. Similarly,
ABM
represents the multi-turn absolute code value,
ABM0
is the lower eight bits of the turn value data,
ABM1
It is the middle eight bits of the circle value data, and
ABM2
is the upper eight bits of the circle value data. If the number of multi-turn code values of the encoder is less than
For 24bit
, the high bits are filled with
0
. So for a high-precision encoder, the encoder will combine the multi-bit single-turn value and the multi-turn value
Each value is divided into
3
bytes of data, and then sent sequentially from the lower eight bits until the sending is completed.