Four pipelined adder 8
Code
//////////////////////////////////////////////////////////////////////////////////
// Company: NanJing University of Information Science & Technology
// Engineer: Yang Cheng Yu
//
// Create Date: 2020/01/21 20:01:50
// Design Name: add_8bit
// Module Name: add_8bit
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//四级流水线8位加法器
module add_8bit(
input clk,
input[7:0] a_in, //8位数输入a
input[7:0] b_in, //8位数输入b
input cin, //进位输入
output reg[7:0] sum_out, //加和输出
output reg cout //进位输出
);
reg c_0to1bit; //0-1位进位输出寄存器
reg[1:0] sum_0to1bit; //0-1位加和输出寄存器
reg c_2to3bit; //2-3位进位输出寄存器
reg[1:0] sum_2to3bit; //2-3位加和输出寄存器
reg c_4to5bit; //4-5位进位输出寄存器
reg[1:0] sum_4to5bit; //4-5位加和输出寄存器
reg c_6to7bit; //6-7位进位输出寄存器
reg[1:0] sum_6to7bit; //6-7位加和输出寄存器
reg[1:0] tempa_2to3bit; //2-3位输入a寄存器
reg[1:0] tempb_2to3bit; //2-3位输入b寄存器
reg[1:0] tempa_4to5bit; //4-5位输入a寄存器
reg[1:0] tempb_4to5bit; //4-5位输入b寄存器
reg[1:0] tempa_6to7bit; //6-7位输入a寄存器
reg[1:0] tempb_6to7bit; //6-7位输入b寄存器
//0-1位加法计算，第一级流水线
always@(posedge clk)begin
{c_0to1bit,sum_0to1bit} <= a_in[1:0] + b_in[1:0] + cin;
tempa_2to3bit <= a_in[3:2];
tempb_2to3bit <= b_in[3:2];
end
//2-3位加法计算，第二级流水线
always@(posedge clk)begin
{c_2to3bit,sum_2to3bit} <= tempa_2to3bit + tempb_2to3bit + c_0to1bit;
tempa_4to5bit <= a_in[5:4];
tempb_4to5bit <= b_in[5:4];
end
//4-5位加法计算，第三级流水线
always@(posedge clk)begin
{c_4to5bit,sum_4to5bit} <= tempa_4to5bit + tempb_4to5bit + c_2to3bit;
tempa_6to7bit <= a_in[7:6];
tempb_6to7bit <= b_in[7:6];
end
//6-7位加法计算，第四级流水线
always@(posedge clk)begin
{c_6to7bit,sum_6to7bit} <= tempa_6to7bit + tempb_6to7bit + c_4to5bit;
end
//最终结果输出
always@(posedge clk)begin
cout <= c_6to7bit;
sum_out <= {sum_6to7bit,sum_4to5bit,sum_2to3bit,sum_0to1bit};
end
endmodule
RTL view
Pipeline used in the present design objective is essentially to carry the output of each one of them registered.
Simulation code
`timescale 1ns/1ps
`define clock_period 20
module add_8bit_tb;
reg clk ;
reg[7:0] a_in ;
reg[7:0] b_in ;
reg cin ;
wire[7:0] sum_out ;
wire cout ;
add_8bit add_8bit(
.clk (clk),
.a_in (a_in),
.b_in (b_in),
.cin (cin),
.sum_out (sum_out),
.cout (cout)
);
initial clk=1;
always#(`clock_period/2)clk=~clk;
initial begin
a_in = 8'b10010010;
b_in = 8'b01001101;
cin = 1'b1;
#(`clock_period*100);
a_in = 8'b11110110;
b_in = 8'b01101001;
cin = 1'b1;
#(`clock_period*100);
$stop;
end
endmodule
Gate-level simulation waveform
As can be seen from the simulation code calculation process takes 86.916ns.
Normal 8-bit adder
Code
module add_8bit_common(
input clk,
input [7:0] a_in,
input [7:0] b_in,
input cin,
output reg cout,
output reg[7:0] sum_out
);
always@(posedge clk)begin
{cout,sum_out} <= cin + a_in + b_in;
end
endmodule
RTL view
Simulation code
`timescale 1ns/1ps
`define clock_period 20
module add_8bit_common_tb;
reg clk ;
reg[7:0] a_in ;
reg[7:0] b_in ;
reg cin ;
wire cout ;
wire[7:0] sum_out ;
add_8bit_common add_8bit_common(
.clk (clk),
.a_in (a_in),
.b_in (b_in),
.cin (cin),
.cout (cout),
.sum_out (sum_out)
);
initial clk=1;
always#(`clock_period/2)clk=~clk;
initial begin
a_in=8'b10010010;
b_in=8'b00011110;
cin=1'b1;
#(`clock_period*100);
a_in=8'b11100010;
b_in=8'b01111010;
cin=1'b1;
#(`clock_period*100);
$stop;
end
endmodule
Gate-level simulation waveform
Calculate the final result of consumption 27.872ns.
If 1000 successive two solutions group data, theoretically ordinary adder takes 27872ns,
pipelined adder takes about 86.916 + 20 * 999 = 20,066.916ns. Thus it can be seen, the pipeline processing method will be higher in a continuous process large quantities of data than the non-pipelined circuit speed, but a small amount of data processing, particularly when the circuit is simple, but the pipeline processing speed will slow.
