Outline
This paper describes the behavior of the hardware, data flow description, the structure described three methods were written several adder
A half adder
That is one of two binary numbers added to obtain a final result of the addition of its normal.
Simulation waveform chart
Hardware behavior description
Designing Documents
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
|
module bjqxw(a,b,sum,cout);
input a,b;
output sum,cout;
reg sum,cout;
always @(a or b)
begin
case({a,b})
2'b00:begin
sum=0;cout=0;
end
2'b01:begin
sum=1;cout=0;
end
2'b10:begin
sum=1;cout=0;
end
2'b11:begin
sum=0;cout=1;
end
endcase
end
endmodule
|
The simulation structure diagram
Simulation files
1
2
3
4
5
6
7
8
9
10
|
module bjqxwsimu;
reg a,b;
wire sum,cout |
Structure Description
Designing Documents
1
2
3
4
5
6
|
module add(a,b,sum,cout);
input a,b;
output sum,cout;
xor(sum,a,b);
and(cout,a,b);
endmodule
|
The simulation structure diagram
Simulation files
1
2
3
4
5
6
7
8
9
10
|
module add1;
reg a,b;
wire sum,cout |
Data flow description
Designing Documents
1
2
3
4
5
6
7
|
endmodulemodule add3(a,b,sum,cout);
input a,b;
output sum,cout;
wire sum,cout;
assign sum=a^b;
assign cout=a&b;
endmodule
|
The simulation structure diagram
Simulation files
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
|
module add1;
reg ain,bin;
reg clk;
wire sum1,cout1;
initial
begin
ain=0;bin=0;clk=0;
end
always #50 clk=~clk;
always @(posedge clk)
begin
ain={$random}%2;
#3 bin={$random}%2;
end
add3 ul(.a(ain),.b(bin),.sum(sum1),.cout(cout1));
endmodule
|
一位全加器
仿真波图
硬件行为描述
设计文件
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
|
module qjq(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
reg sum,cout;
always @(a or b or cin)
begin
case ({cin,a,b})
3'b000:begin
sum=0;cout=0;
end
3'b001:begin
sum=1;cout=0;
end
3'b010:begin
sum=1;cout=0;
end
3'b011:begin
sum=0;cout=1;
end
3'b100:begin
sum=1;cout=0;
end
3'b101:begin
sum=0;cout=1;
end
3'b110:begin
sum=0;cout=1;
end
3'b111:begin
sum=1;cout=1;
end
endcase
end
endmodule
|
仿真结构图
仿真文件
1
2
3
4
5
6
7
8
9
10
|
module qjq1;
reg a,b,cin;
wire sum,cout;
qjq ul(a,b,cin,sum,cout);
initial
begin
a=0;b=0;cin=0;
end
always #10 {a,b,cin}={a,b,cin}+1;
endmodule
|
结构描述
设计文件
1
2
3
4
5
6
7
8
9
10
|
module qiq(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
wire q1,q2,q3;
xor(sum,a,b,cin);
or(q1,a,b);
or(q2,b,cin);
or(q3,a,cin);
and(cout,q1,q2,q3);
endmodule
|
仿真结构图
仿真文件
1
2
3
4
5
6
7
8
9
10
|
module qjq1;
reg a,b,cin;
wire sum,cout;
qiq ul(a,b,cin,sum,cout);
initial
begin
a=0;b=0;cin=0;
end
always #10 {a,b,cin}={a,b,cin}+1;
endmodule
|
数据流描述
设计文件
1
2
3
4
5
|
module qjq(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
assign {sum,cout}=a+b+cin;
endmodule
|
仿真结构图
仿真文件
1
2
3
4
5
6
7
8
9
10
|
module qjqsimu |
四位全加器
数据流描述
设计文件
1
2
3
4
5
6
7
|
module qjq(a,b,cin,sum,cout);
input [3:0] a,b;
input cin;
output [3:0] sum;
output cout;
assign {sum,cout}=a+b+cin;
endmodule
|
仿真结构图
仿真文件
1
2
3
4
5
6
7
8
9
10
11
12
|
module qjqsimu;
reg [3:0] a,b;
reg cin;
wire [3:0] sum;
wire cout;
qjq sl(a,b,cin,sum,cout);
initial
begin
a=4'b0000;b=4'b0000;cin=0;
end
always #20 {a,b}={a,b}+4'b0001;
endmodule
|
仿真波图
ps：将上述输入输出的字段长度对应修改，可得到相应数位的全加器数据流描述