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1. Half adder
A half adder is a basic logic circuit used to sum two input bits. It has two input bits, A and B, and two output bits, Sum and Carry.
Code:
/*
* @Description: 一位半加器实现，半加器是指对输入的两个一位二进制数相加（A与B），输出一个结果位（SUM）和进位（C），
没有进位的输入加法器电路，是一个实现一位二进制数的加法电路。
* @Author: Fu Yu
* @Date: 2023-07-20 19:33:10
* @LastEditTime: 2023-07-21 10:50:44
* @LastEditors: Fu Yu
*/
module adder (
input wire A ,
input wire B ,
output wire SUM ,//输出本位和
output wire Cout //输出进位
);
//第一种方法
assign SUM = A^B;
assign Cout = A&B;
// //第二种
// assign {Cout,sun} = A + B;
endmodule //adder
Test file:
/*
* @Description: 半加器测试文件
* @Author: Fu Yu
* @Date: 2023-07-20 19:44:01
* @LastEditTime: 2023-07-21 10:03:32
* @LastEditors: Fu Yu
*/
`timescale 1ns/1ns
module adder_tb();
//定义激励信号
reg tb_A;
reg tb_B;
//定义输出信号
wire tb_SUM;
wire tb_Cout;
//模块实例化
adder u_adder(
. A (tb_A) ,
. B (tb_B) ,
. SUM (tb_SUM) ,
. Cout (tb_Cout)
);
initial begin
tb_A = 0;
tb_B = 0;
#1;
tb_A = 1;
tb_B = 0;
#1;
tb_A = 0;
tb_B = 1;
#1;
tb_A = 1;
tb_B = 1;
#1;
end
endmodule
Two, 1-bit full adder
The 1-bit full adder further adds an input bit Carry-In (carry input) on the basis of the half adder to process the carry from the previous bit. It has three input bits A, B, and Carry-In, and two output bits Sum and Carry-Out. 
Code:
/*
* @Description: 1位全加器设计
* @Author: Fu Yu
* @Date: 2023-07-21 10:55:36
* @LastEditTime: 2023-07-21 23:28:26
* @LastEditors: Fu Yu
*/
module full_adder(
input wire x ,
input wire y ,
input wire cin ,//低位的进位
output wire s ,//本位的和
output wire cout //进位
);
//第一种
assign {cout , s} = x + y + cin;
// //第二种
// assign s = x^y^cin;
// assign cout = (x&y)|(y&cin)|(x&cin);//(x&y) | (x^y&cin)
endmodule
Test file:
/*
* @Description: 1位全加器测试文件
* @Author: Fu Yu
* @Date: 2023-07-21 12:13:35
* @LastEditTime: 2023-07-21 13:34:30
* @LastEditors: Fu Yu
*/
`timescale 1ns/1ns
module full_adder_tb();
//激励信号的定义
reg tb_x;
reg tb_y;
reg tb_cin;
//输出信号的定义
wire tb_s;
wire tb_cout;
initial begin
repeat(10)begin
tb_x = {$random}%2;
tb_y = {$random}%2;
tb_cin = {$random}%2;
#1;
end
end
full_adder u_full_adder(
. x (tb_x) ,
. y (tb_y) ,
. cin (tb_cin) ,//低位的进位
. s (tb_s) ,//本位的和
. cout (tb_cout) //进位
);
endmodule
Three, n-bit full adder
The n-bit full adder is a logic circuit that connects multiple 1-bit full adders together to realize the addition of n-bit binary numbers. It consists of n 1-bit full adders and a carry input (Carry-In) of the most significant bit (Most Significant Bit, MSB). The carry-in of each 1-bit full adder comes from the carry-out of the previous 1-bit full adder.
Code design:
/*
* @Description: n位全加器设计
* @Author: Fu Yu
* @Date: 2023-07-21 13:38:31
* @LastEditTime: 2023-07-21 23:27:44
* @LastEditors: Fu Yu
*/
module adder_Nbit #(parameter N = 8)(
input wire [N-1:0] x ,
input wire [N-1:0] y ,
input wire cin ,
output wire cout ,
output wire [N-1:0] sum
);
// assign {cout,sum} = x + y + cin;
wire [N:0] C;
genvar i;
generate
for(i=0;i<N;i=i+1)
begin :my_adder//实例化循环名字
full_adder u_full_adder(
. x (x[i]),
. y (y[i]),
. cin (C[i]),
. s (sum[i]),
. cout (C[i+1])
);
end
endgenerate
assign C[0] = cin;//第一个全加器输入
assign cout = C[N];//输出最高的进位
endmodule
Test file:
/*
* @Description: n位全加器仿真
* @Author: Fu Yu
* @Date: 2023-07-21 23:08:10
* @LastEditTime: 2023-07-21 23:11:39
* @LastEditors: Fu Yu
*/
`timescale 1ns/1ns
module adder_Nbit_tb();
parameter N = 6;
//定义激励信号
reg [N-1:0] tb_x;
reg [N-1:0] tb_y;
reg tb_cin;
//定义输出信号
wire tb_cout;
wire [N-1:0] tb_sum;
initial begin
tb_cin = 0;
repeat(10)begin
tb_x = {$random}%(2**(N-1));
tb_y = {$random}%(2**(N-1));
#1;
end
end
adder_Nbit #(.N(N)) u_adder_Nbit(
. x (tb_x) ,
. y (tb_y) ,
. cin (tb_cin) ,
. cout (tb_cout) ,
. sum (tb_sum)
);
endmodule
