Table of contents
3. Validate the two-choice data selector
Fourth, verify the 2-4 decoder
0 decides and, 1 decides or .
1. Verify AND gate
As long as a button is pressed, the result is a low level and the light is on.
assign led1 = key1&key2; //与门（只要有一个按键按下，则结果为低电平，灯亮）//验证与门、与非门
module my_and //my_and：文件名称
(
//1、配置输入输出变量
input wire key1, //输入引脚key1
input wire key2, //输入引脚key2
output wire led1, //输出引脚led1
output wire led2 //输出引脚led2
);
//2、变量赋值
assign led1 = key1&key2; //与门（只要有一个按键按下，则结果为低电平，灯亮）
//assign led2 = !(key1&key2); //与非门（没有按键按下，全为1，结果取反，为0，,灯亮）
endmoduleSecond, verify the NAND gate
Two numbers are ANDed and negated.
Only when no button is pressed, both buttons are 1, and the result of the phase AND is 1, and then the inversion is 0, and the final level lights up. (If any button is pressed, the light will not light up)
assign led2 = !(key1&key2); //与非门（没有按键按下，全为1，结果取反，为0，,灯亮）//验证与门、与非门
module my_and //my_and：文件名称
(
//1、配置输入输出变量
input wire key1, //输入引脚key1
input wire key2, //输入引脚key2
output wire led1, //输出引脚led1
output wire led2 //输出引脚led2
);
//2、变量赋值
//assign led1 = key1&key2; //与门（只要有一个按键按下，则结果为低电平，灯亮）
assign led2 = !(key1&key2); //与非门（没有按键按下，全为1，结果取反，为0，,灯亮）
endmodule3. Validate the two-choice data selector
sl is the screening end, a and b are two input ends .
//二选一数据选择器
module my_and(led1, key1, key2, key3);
input wire key1, key2, key3; //输入：a、b、s
output reg led1; //输出(y/out)
always@(key1, key2, key3)
begin
//使能按下
if(!key3)
led1 = key1;
else
led1 = key2;
end
endmoduleFourth, verify the 2-4 decoder
2-4: Realized by 1+2 buttons and 4 LED lights.
Enable it first. (enable button E)
Four states of two buttons: 00, 01, 10, 11 .
Button 00:1 (led1 is on)
button 01:2 (led2 is on)
button 10:3 (led3 is on)
button 11:4 (led4 is on)
//2-4线译码器
module my_and(key, led, E);
input wire[1:0] key; //定义两个key数组
input wire E; //定义使能按键
output reg[3:0] led=4'b1111; //定义四个led数组(赋初值1)(熄灭led)
always@(key)
//使能按键按下
if(!E)
begin
case(key)
2'b00: led = 4'b0111; //按键00:1(led1亮)
2'b01: led = 4'b1011; //按键01:2(led2亮)
2'b10: led = 4'b1101; //按键10:3(led3亮)
2'b11: led = 4'b1110; //按键11:4(led4亮)
default: led = 4'b1111; //led全灭（出错）
endcase
end
endmodule5. Verify the half adder
Half Adder: Adds two input data bits and outputs a result bit plus a carry.
Result: S = A ^ B (S=A XOR B)
Carry: C = A & B (C=A and B)
Define 2 key inputs: A, B (representing two inputs A, B respectively)
Define 2 LED outputs: S, C (respectively represent the standard result S, carry C)
//验证半加器
module my_and(A, B, S, C);
input wire A, B; //定义两个输入
output wire S, C; //定义结果、进位输出
assign S = A^B; //本位结果S=A异或B
//二进制只有0+1 或 1+0 才有结果1；否则1+1或者0+0，当前位都为0
assign C = A&B; //进位C=A与B
//二进制只有1+1 才会出现进位
endmoduleSixth, verify the full adder
Full adder: Two half adders connected together .
Labeled 1st and 2nd stage half adders:
(The red mark is the place where it is easy to make a mistake)
A, B, and CI are inputs, and the result bit S and carry CO are outputs .
Using module instantiation, two half adders are instantiated separately, and finally combined into a full adder .
0. Initialization definition
Define input and output pin variables.
//全加器（两个半加器连接）
module my_and(A, B, Ci, S, Co);
//变量定义
input wire A, B, Ci; //输入1、输入2、低端进位（输入3）
output wire S, Co; //结果输出位、总进位1. The first half adder
The two keys key1 and key2 represent A and B respectively, as two inputs. The final result bit is used as A2 (the second, that is, the latter half adder), and the carry bit is obtained as C1 .
Note: When the module is instantiated, the input is passed in (assigned in), and the output is passed out (assigned) .
The half adder half_adder only needs to put the .v file into the folder (written earlier).
//模块实例化（此处采样端口关联）
//第一个半加器
half_adder half_adder1(.A(A), .B(B), .S(A2), .C(C1));
//第一个半加器： 输入1 输入2 结果位(输出) 进位(输出)2. The second half adder
A2 is the first S result bit, which is used as the input 1 of the second half adder, and the low-end carry Ci corresponds to the button key3, which is used as the input 2 of the second half adder. The final result S and the second half adder carry C2 are respectively obtained .
//第二个半加器
half_adder half_adder2(.A(A2), .B(Ci), .S(S), .C(C2));
//第二个半加器： 输入1 输入2(低端进位) 结果位(输出) 进位(输出)3. Get the final carry Co
The second half adder has already obtained the final S result bit, so now it only needs to process the final carry Co.
Combine (or) the carries C1 and C2 of the two half adders to get the final carry Co:
//总进位
assign Co = C1 | C2;the code
//全加器（两个半加器连接）
module my_and(A, B, Ci, S, Co);
//变量定义
input wire A, B, Ci; //输入1、输入2、低端进位（输入3）
output wire S, Co; //结果输出位、总进位
//模块实例化（此处采样端口关联）
//第一个半加器
half_adder half_adder1(.A(A), .B(B), .S(A2), .C(C1));
//第一个半加器： 输入1 输入2 结果位(输出) 进位(输出)
//第二个半加器
half_adder half_adder2(.A(A2), .B(Ci), .S(S), .C(C2));
//第二个半加器： 输入1 输入2(低端进位) 结果位(输出) 进位(输出)
//注：和输入端口相关联时，传入值（赋值进去）；
// 和输出端口相关联时，传出值（赋值出来）。
//总进位
assign Co = C1 | C2;
endmodule