An improved method for designing chaotic signal generator based on FPGA is proposed. First, the Euler algorithm is used to transform the continuous chaotic system into a discrete chaotic system. Secondly, based on the IEEE-754 single-precision floating-point number standard and modular design concept, the Quartus II software is used to design the chaotic signal generator using a combination of VHDL and schematic diagrams. Finally, the experiment is carried out on the FPGA experimental system, and the phase diagram of the chaotic attractor and the chaotic signal in the domain are displayed on the oscilloscope. Due to the area optimization method based on the data selector, the floating-point arithmetic module that consumes more logic resources is reused, which greatly reduces the FPGA logic resources occupied by the chaotic signal generator . The experimental results prove the effectiveness and versatility of the method.
0 Preface
Using discrete component analog electronic circuits to generate chaotic signals is currently the most commonly used method [1,2], but components are prone to aging, and system changes are not flexible. Therefore, people consider whether digital devices (such as FPGA) can be used instead of analog components to complete the response. To improve the flexibility, security and practicability of the chaotic secure communication system design. Aseeri, MA et al. [3] proposed a method to implement Lorenz chaotic system with FPGA technology. Zhang Yu et al. [4] proposed a new method of generating multi-scroll hyperchaotic attractors using FPGA technology. Wang Zhonglin et al. [5] proposed a method to realize chaotic attractor based on FPGA platform and EDA development tools. The literature [3,4,5] uses DSP Builder technology instead of hardware description language implementation according to the IEEE-754 standard. Its main disadvantage is that it cannot fundamentally solve problems such as timing control. In chaotic synchronization and Its application in confidential communication is restricted. Zhou Wujie et al. [6] proposed a new method for the design and hardware implementation of a field programmable gate array (FPGA) general chaotic and hyperchaotic signal generator based on the IEEE-754 standard. This method has the advantage of strong versatility and fundamentally solves the timing control problem. However, in this method, the programming of the floating-point arithmetic module is more difficult and the chaotic system occupies more FPGA logic resources. This article has made two improvements on the basis of literature [6]: (1) Using the megafunctions of floating-point multiplier and adder/subtractor provided by QuartusⅡ, customize floating-point arithmetic module to meet the design requirements without Programming reduces the difficulty of design and improves design efficiency. (2) The area optimization method based on the data selector is used to reuse the floating-point arithmetic module that consumes more logic resources. Based on the Altera EP1C3T144C8 chip (containing only 2910 logic units), the Lorenz, Chen, and Chua chaos are successfully designed and implemented. Signal generator. For convenience, this article takes the design and implementation of Lorenz chaotic signal generator as an example.
The IEEE-754 single-precision floating-point number format [7] is 32 bits, as shown in Figure 1.
| 31 |
30 23 |
22 0 |
| S |
E |
F |
Figure 1 Single-precision floating-point number format
Among them, the 31st bit is the sign bit (S), the 30th to 23rd bits are the 8-bit order code (E), the 22nd to 0th bits are the 23-bit mantissa (F), the offset value is 127, and the mantissa has one bit Hidden bits. For normalized numbers, 0<E<255, and the value V=(-1)S×2E-127×1.F.
(3) The correspondence between the decimal format of the constant in the formula and the IEEE-754 single-precision format is listed in Table 1.
Table 1 Correspondence between decimal format and single precision format of system parameters
| Decimal |
Single precision |
Decimal |
Single precision |
| 0.99 |
3F 7D70A3 |
0.999 |
3F 7FBE76 |
| 0.01 |
3C 23D70A |
0.001 |
3A83126E |
| 0.028 |
3CE56041 |
0.9973333 |
3F 7F 513C |
According to formula (3), the main design concept of using FPGA technology to design Lorenz chaotic system is to divide the whole system into several basic functional modules, mainly including floating-point multiplier, floating-point adder/subtractor, data selector, and data distributor , Timing control module and numerical conversion module and other main modules. Now make a brief analysis.
3.1 Floating point multiplier and floating point adder/subtractor
It can be seen from the formula (3) that to realize the Lorenz chaotic system, floating-point multiplier and floating-point adder/subtractor are indispensable. Using the megafunctions of floating-point multiplier and adder/subtractor provided by QuartusⅡ, floating-point arithmetic modules can be customized to meet the design requirements without programming, which is simple and easy to implement, reduces design difficulty and improves design efficiency.
The floating-point multiplier and floating-point adder/subtractor are stored in the altera/72/quartus/libraries/megafunctions/arithmetic folder under the installation directory of the Quartus II software, and their names are altfp_mult and altfp_add_sub, respectively. The user can use the MegaWizard wizard to generate practical circuit modules and define the parameters of the megafunction. In this design, the floating-point multiplier and floating-point adder/subtractor both adopt the 32-bit single-precision floating-point number format of IEEE-754, and the output response time is 10 clk cycles, occupying 1399 and 697 logic units respectively.
3.2 Data selector
It can be seen from equation (3) that for a complete iterative calculation, 8 floating-point multiplication operations are required (because 0.001x(n-1) only needs to be calculated once) and 4 floating-point addition or subtraction operations. In addition, because the variable x∈(-20,20) of the Lorenz chaotic system needs to be added with a constant (such as 20) to become a non-negative number, so that the unipolar DA converter can output analog signals, so it needs to be done One addition operation. Obviously, if it is not optimized, only the floating-point arithmetic unit will occupy 1399×8+697×5=14677 logic units.
In order to reduce the usage of FPGA chip logic resources and also reduce the power consumption of the chip, this design adopts the area optimization method based on the data selector. The main idea is to use the advantage of speed in exchange for area saving. When the operating frequency of the system allows, for modules that consume more logic resources in the data path, multiplexing is performed through multiple selection methods to reduce the use of this module. The number can achieve the purpose of reducing resource usage and optimizing area.
This design is based on the above-mentioned area optimization idea. It uses 4 32-bit 8-to-1 data selectors to multiplex a floating-point multiplier and a floating-point adder/subtractor. It is finally based on the Altera EP1C3T144C8 chip (with only 2910 logic Unit) successfully implemented the Lorenz chaotic system.
3.3 Data distributor
The function of the data distributor and the data selector is exactly the opposite. It is used to distribute the results of floating-point multiplication and floating-point addition/subtraction to the corresponding data registers for registration. Although Quartus II software does not have a ready-made data distributor module, it can be designed and implemented by VHDL programming.
3.4 Timing control module
The timing control module provides timing control signals for the floating-point multiplier, floating-point adder/subtractor, data selector, data distributor and other modules to coordinate the orderly work of each module.
The timing control module is implemented by finite state machine programming and is composed of 13 states. In order to ensure that there is enough time to complete floating-point operations, the retention time of each state is 11 clk cycles. When programming, it is best to use a single-process state machine that describes the status register, secondary state logic, and output logic in one process, so that the output signal is latched and output synchronously by the sequential device, which can well improve the glitch phenomenon.
The timing simulation result of the timing control module is shown in Figure 2.
Figure 2 Timing simulation results of the timing control module
In Figure 2, clk is the clock input signal, reset is the reset input signal, and the rest are output signals. Among them, sel is the selection signal of the data selector and data distributor, mul is the floating-point multiplier enable signal, and clk0~clk12 are 13 Clock signal of a 32-bit data register. It can be seen from the figure that there is no glitch in the output signal.
3.5 Numerical Conversion Module
FPGA can only output digital signals, and an external digital-to-analog converter must be connected to convert digital signals to analog signals. The 10-bit DA converter THS5651 is used in this design. The numerical conversion module is used to convert 32-bit single-precision floating-point numbers into 10-bit digital quantities. Only in this way can FPGA be connected to THS5651.
(3) The state variables x∈(-20,20), z∈(0,50) of the Lorenz chaotic system described by formula. In order to facilitate the output of the analog signal from the unipolar DA converter, the state variable x of the Lorenz chaotic system needs to be added by 20, which is recorded as x', then x', z∈(0,50), its 32-bit single-precision floating point format The maximum value of the order code should be 10000100.
The numerical conversion module adopts VHDL programming to realize, its input datain (31downto 0) and output data dataout (9 downto 0) the correspondence relation as shown in table 2.
Table 2 Correspondence between 32-bit floating-point numbers and 10-bit digital quantities
| datain(30 downto 23) |
dataout(9 downto 0) |
| "10000100" |
"1" & datain(22 downto 14) |
| "10000011" |
"01" & datain(22 downto 15) |
| "10000010" |
"001" & datain(22 downto 16) |
| "10000001" |
"0001" & datain(22 downto 17) |
| "10000000" |
"00001" & datain(22 downto 18) |
| "01111111" |
"000001" & datain(22 downto 19) |
| "01111110" |
"0000001" & datain(22 downto 20) |
| "01111101" |
"00000001" & datain(22 downto 21) |
| "01111100" |
"000000001" & datain(22) |
| "01111011" |
"0000000001" |
| others |
"0000000000" |