1. The basic concept of DDS
DDS (Direct Digital Synthesizer), a direct digital frequency synthesizer, is a key digital technology. Compared with the traditional frequency synthesis technology, it has the advantages of low cost, low power consumption, high resolution and good phase continuity, etc., and is widely used in the communication field. DDS can be used to synthesize signal waveforms with controllable phase, frequency and amplitude.
2. Principle of DDS
The above figure is the basic structure diagram of DDS. It can be seen that DDS is mainly composed of phase accumulator, phase adder, waveform lookup table and D/A conversion.
The waveform lookup table is generally a ROM, which stores the sampling value of the signal. This time it stores a sine signal, but it also supports square wave and triangle wave and other signal waveforms. For the waveform lookup table, given an address, the waveform data corresponding to the address can be read out, and this series of discrete data forms the target waveform, and then the digital-to-analog conversion is performed to obtain a continuous waveform.
Assuming that the number of bits of the phase accumulator is N bits (N=32 in this experiment), it is equivalent to dividing the phase of the sinusoidal signal into parts, and its resolution is 1/
.
The frequency control word fword is used to control the step size of each self-increment of the behavior control word. When it is 1, the phase of each clock cycle is increased by 1 to output the frequency. If fword=B, the phase of each clock cycle The self-increasing step size is B, and its output frequency is
, where B must be an integer.
When the phase control word pword is 0, by accumulating the frequency control word fword in the phase accumulator, the address of the waveform lookup table ROM can be obtained, and then the value corresponding to this address can be taken out to obtain the output waveform data . But in order to control the phase, we directly add the value of the phase control word pword to the output of the phase accumulator, which is equivalent to making an offset to the ROM address as a whole, thus completing the phase change.
In practical applications, in order to reasonably control the capacity of the ROM, when converting the result of adding the phase accumulator and the phase control word into the query address of the ROM, we use the truncation method, and only use the high M value of the 32-bit phase accumulator. bit, in this experiment, M=32. That is, the address of ROM is 16 bits, and its depth is .
3. Design of DDS
After clarifying the composition of DDS, we can complete the hardware description of DDS by constructing according to the diagram.
The first is the synchronization register of the frequency control word. We use a register to save the value of the frequency control word fword for one clock cycle. Next is the phase accumulator, which is also a register. Each time the result of the phase accumulator is added to the frequency control word The value of the phase control word is the same; the synchronous register of the phase control word is the same as the former, and the result is added to the output result of the phase accumulator, and the change of the initial phase can be realized, that is, the query address of the ROM is shifted; finally, the The high 16 bits of the phase accumulator result are summed with the phase accumulator as the address of the ROM, and the corresponding target waveform can be output by sending the address to the ROM.
`timescale 1ns / 1ps
module DDS(
//input
clk ,
rst_n,
fword,
pword,
hword,
//output
wave_out,
read_addr
);
input clk ;
input rst_n;
input [31:0] fword;
input [15:0] pword;
input [1:0 ] hword;
output reg signed [15:0] wave_out;
output [15:0] read_addr;
//幅度定义：1,1/2,1/4,1/8,
parameter h1 = 2'b00 ;
parameter h2 = 2'b01 ;
parameter h3 = 2'b10 ;
parameter h4 = 2'b11 ;
//频率控制字同步寄存器
reg [31:0] fword_r;
always@(posedge clk or negedge rst_n)
if(!rst_n)
fword_r <= 32'd0;
else
fword_r <= fword;
//相位控制字同步寄存器
reg [15:0] pword_r;
always@(posedge clk or negedge rst_n)
if(!rst_n)
pword_r <= 16'd0;
else
pword_r <= pword;
//相位累加器
reg [31:0] p_sum;
always@(posedge clk or negedge rst_n)
if(!rst_n)
p_sum <= 16'd0;
else
p_sum <= p_sum + fword_r;
//波形查找表ROM的地址
reg [15:0] read_addr;
always@(posedge clk or negedge rst_n)
if(!rst_n)
read_addr <= 16'd0;
else
read_addr <= p_sum[31:16] + pword_r;
wire [15:0] wave;
blk_mem_gen_0 blk_mem_gen_0(
.clka (clk),
.ena (rst_n),
.addra(read_addr),
.douta(wave)
);
always@(posedge clk or negedge rst_n)
if(!rst_n)
wave_out <= 16'd0;
else
case(hword)
h1:wave_out = wave - 16'd32767 ;
h2:wave_out = (wave - 16'd32767)/2;
h3:wave_out = (wave - 16'd32767)/4;
h4:wave_out = (wave - 16'd32767)/8;
default:wave_out = wave - 16'd32767;
endcase
endmodule
The configuration of the ROM is as follows:
The initialization file of the ROM is a sine wave, which can be generated with a tool, or the file I used can be used directly. (6 messages) ROM initialization file, sine wave resource - CSDN library 
https://download.csdn.net/download/qq_57541474/87886533
4. Simulation
Fclk=50MHZ，Fo=B*Fclk/2^32,ROM的width=16,depth=65536=2^16。
Simulations were performed for three different frequencies and the results were as expected.
1.waveA:fword=8192=2^13,pword=0°，T=10.48576ms，f=95.3674,Fo=Fclk/2^19=95.3674。
2.waveB: fword=8192=2^13,pword1=16384=90°fword2=32768=180°，T=10.48576ms，f=95.3674,Fo=Fclk/2^19=95.3674。
The frequency of signal A and B is the same, the phase of channel A remains unchanged, and the signal phase of channel B is at 1/4 depth, that is, 90 °, and then becomes 1/2 depth, that is, 180 °, as can be seen from the simulation results The phase difference is correct, and the frequency is the same as the second time above.