Design of Parallel Multiplier Based on FPGA Verilog

Parallel Multiplier
Advantages: relatively fast
Disadvantages: high resource consumption

    module mult(
	
	    input    clk,
		input    rst_n,
	    input    [7:0]mul_a, 
		input    [7:0]mul_b, 
		
		output   reg[15:0]mul_out
	);

    reg [15:0] stored0;
    reg [15:0] stored1;
    reg [15:0] stored2;
    reg [15:0] stored3;
	reg [15:0] stored4;
    reg [15:0] stored5;
    reg [15:0] stored6;
    reg [15:0] stored7;

    reg [15:0] add01;
    reg [15:0] add23;
	reg [15:0] add45;
	reg [15:0] add67;

    reg [15:0] add0123;
	reg [15:0] add4567;

    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            mul_out <= 0;
            stored0 <= 0;
            stored1 <= 0;
            stored2 <= 0;
            stored3 <= 0;
            add01 <= 0;
            add23 <= 0;
        end
        else begin
            stored0 <= mul_b[0]? {8'b0, mul_a      } : 16'b0;
            stored1 <= mul_b[1]? {7'b0, mul_a, 1'b0} : 16'b0;
            stored2 <= mul_b[2]? {6'b0, mul_a, 2'b0} : 16'b0;
            stored3 <= mul_b[3]? {5'b0, mul_a, 3'b0} : 16'b0;
			
			stored4 <= mul_b[4]? {4'b0, mul_a, 4'b0} : 16'b0;
			stored5 <= mul_b[5]? {3'b0, mul_a, 5'b0} : 16'b0;
			stored6 <= mul_b[6]? {2'b0, mul_a, 6'b0} : 16'b0;
			stored7 <= mul_b[7]? {1'b0, mul_a, 7'b0} : 16'b0;
			

            add01 <= stored0 + stored1;
            add23 <= stored2 + stored3;
			
			add45 <= stored4 + stored5;
			add67 <= stored6 + stored7;
			
			add0123 <= add01 + add23;
			add4567 <= add45 + add67;
			
            mul_out <= add0123 + add4567;
        end
    end

endmodule

Simulation: (only three cycles delayed, the speed is still relatively fast)