First, we use MATLAB to simulate and get the following results:
Then we use FPGA to implement
At this time, A=10, B=28, and C=8/3 are typical parameters.
In order to facilitate the realization of continuous chaotic systems with FPGA, the Euler algorithm can be used to discretize the equation to obtain the following discretization equation:
In this system, we use the IEEE754 single-precision representation method for representation, and the following results can be obtained.
0.99 3F7D70A3
0.999 ： 3F7FBE76
0.01 ： 3C23D70A
0.001 ： 3A83126E
0.028 ： 3CE56041
0.9973333 ： 3F7F513C
2.1 Floating point multiplier
The multiplier, we use the IP core to complete.
Figure 1 Multiplier IP core generation step 1
Next step:
Figure 2 Step 2 of multiplier IP core generation
Next step:
Figure 3 Multiplier IP core generation step 3
Keep the default settings for the rest.
Complete, simulate the core, the simulation results are as follows:
Figure 4 Multiplier IP core simulation
2.2 Floating point adder / subtractor
Figure 5 Adder IP core generation
Leave the rest as default and complete the setting of the adder IP core.
The simulation results are as follows:
Figure 6 IP core simulation of the adder
All the top-level schematics are as follows:
From the above, we can see that the entire system takes up less resources, mainly practical to a large number of multipliers.
4 system simulation
Perform functional simulation of the system: get the following results:
Figure 13 Overall system simulation results