·In this topic, the floating-point operation is converted into a large-bit wide binary calculation, which not only simplifies the calculation process, but also ensures the accuracy of the algorithm.
·By looking at the relevant information, there are three ways of chaos encryption: superposition, multiplication and linear operation, but there is no XOR, so here, we use chaos superposition to encrypt.
·Some modules cannot be individually written as modules for design needs, so we try to write clearly how to design them in the documentation.
The basic structure of this system, we follow the structure provided by you, the whole block diagram is as follows:
First realize the simulation of the algorithm using MATLAB, the simulation results we get are as follows:
This is the basic simulation of the chaos model, which shows the correctness of the formula and initial value selection.
This program is the MATLAB floating-point simulation result diagram of the chaotic encryption modulation and demodulation system, indicating that the above result is correct.
It can be seen from the above simulation results that if the simulation is performed at a fixed point, as long as the quantization width meets certain requirements, it does not affect the accuracy of the system at all.
According to the above introduction, we can write the following program:
From top to bottom, in order:
System top file
——Encryption Modulation Module
————Encryption sub-module, lorenz chaotic sequence generation module, framing module, parallel serial module.
——Decryption demodulation module
——Decryption sub-module, Lorenz chaotic sequence generation module, frame search module, serial-parallel module.
Each module is introduced below.
| System top file ——Encryption Modulation Module ————Encryption sub-module, lorenz chaotic sequence generation module, framing module, parallel serial module. ——Decryption demodulation module ——Decryption sub-module, Lorenz chaotic sequence generation module, frame search module, serial-parallel module. |
The meanings of the interfaces are:
System clock
System reset
Test parallel signal generation enable signal
Test parallel signals
Enabling signal of encryption module
Serial output
Serial signal framing output
Encrypted output
Decrypt output
Deciphering the sign decision of the output signal
Correlation peak output of frame search module
Enable output of frame search module
Data output of search frame module
Enable the final serial-parallel conversion
The final serial and parallel converted data output
The top module, the main function is to generate test data, 16-bit wide parallel data:
Then call the encryption modulation module and decryption demodulation module respectively:
The specific interface meaning, we will explain when introducing these sub-modules.
| System top file - encryption modulation module ————Encryption sub-module, lorenz chaotic sequence generation module, framing module, parallel serial module. ——Decryption demodulation module ——Decryption sub-module, Lorenz chaotic sequence generation module, frame search module, serial-parallel module. |
The interface meaning of the encryption module is
Clock, reset, input parallel signal enable signal, input parallel signal, serial output, output after framing, encrypted signal:
among them:
The encrypted output signal o_T_signal is fed back to the lorenz chaos module for iteration, and the iterated yn output is encrypted.
| System top file ——Encryption Modulation Module ———— Encryption sub-module , lorenz chaotic sequence generation module, framing module, parallel serial module. ——Decryption demodulation module ——Decryption sub-module, Lorenz chaotic sequence generation module, frame search module, serial-parallel module. |
They are system clock, reset, data input, chaotic y output, and encrypted signal output.
The basic principle is realized by superposition of signal and chaotic signal.
| System top file ——Encryption Modulation Module ————Encryption sub-module, lorenz chaotic sequence generation module , framing module, parallel serial module. ——Decryption demodulation module ——Decryption sub-module, Lorenz chaotic sequence generation module, frame search module, serial-parallel module. |
Its interface is
System clock, reset, encrypted feedback signal, chaotic xyz output.
Note that here we use a fixed-point calculation method based on the floating-point principle. Because the floating-point calculation algorithm directly used in the FPGA is more complicated and resource-consuming, the traditional fixed-point calculation accuracy is not enough. Therefore, here we use The fixed-point calculation of floating point is a method of expanding the bit width and performing truncation after multiplying.
Through this idea, the lorenz algorithm can be transformed into:
// y (n + 1) = 0.028 * x (n) - 0.001 * x (n) * z (n) + 0.999 * y (n);
// x (n + 1) = 0.99 * x (n) + 0.01 * y (n);
//z(n+1) = 0.001*x(n)*y(n) + 0.9973333*z(n);
// y (n + 1) = 1835 * x (n) - 66 * x (n) * z (n) + 65470 * y (n);
// x (n + 1) = 64881 * x (n) + 655 * y (n);
//z(n+1) = 66*x(n)*y(n) + 65361*z(n);
| System top file ——Encryption Modulation Module ————Encryption sub-module, lorenz chaotic sequence generation module, framing module , parallel serial module. ——Decryption demodulation module ——Decryption sub-module, Lorenz chaotic sequence generation module, frame search module, serial-parallel module. |
The interfaces are system clock, reset, serial data input, data enable, data output, and data output enable.
The main function of adding the framing module here is
在接收端，当解调出正确的信号的时候，我们无法知道何时进行串并转化才能够得到正确的并行信号，即我们无法知道数据哪位是起始位置。
所以加入帧头之后，在接收端进行帧头搜索，我们就可以得到数据的起始位置。
这里，我们的做法是在数据头部加入连续的训练序列。组帧后的数据格式如下所示：
其中前面的h就是多个训练序列，后面的data就是实际的信号数据。
| 系统顶层文件 ——加密调制模块 ————加密子模块，lorenz混沌序列产生模块，组帧模块，并串模块。 ——解密解调模块 ————解密子模块，Lorenz混沌序列产生模块，搜帧模块，串并模块。 |
分别为系统时钟，复位，数据使能，并行数据，串行数据使能，串行数据。
其基本原理是通过计数器的方式进行的。这里就不多做介绍了。
| 系统顶层文件 ——加密调制模块 ————加密子模块，lorenz混沌序列产生模块，组帧模块，并串模块。 ——解密解调模块 ————解密子模块，Lorenz混沌序列产生模块，搜帧模块，串并模块。 |
其接口分别为
系统时钟
复位
接收到的加密信号
解密输出
解密输出的判决信号
搜帧模块的相关峰输出
搜帧模块的使能输出
搜帧模块的数据输出
最后串并转化的使能
最后串并转化的数据输出
| 系统顶层文件 ——加密调制模块 ————加密子模块，lorenz混沌序列产生模块，组帧模块，并串模块。 ——解密解调模块 ————解密子模块，Lorenz混沌序列产生模块，搜帧模块，串并模块。 |
接口为时钟，复位，输入信号，混沌信号yn，解密输出。
其基本原理为想减计算。
| 系统顶层文件 ——加密调制模块 ————加密子模块，lorenz混沌序列产生模块，组帧模块，并串模块。 ——解密解调模块 ————解密子模块，Lorenz混沌序列产生模块，搜帧模块，串并模块。 |
这个模块和发送端的相同。
| 系统顶层文件 ——加密调制模块 ————加密子模块，lorenz混沌序列产生模块，组帧模块，并串模块。 ——解密解调模块 ————解密子模块，Lorenz混沌序列产生模块，搜帧模块，串并模块。 |
接口为时钟，复位，输入解密后的数据，搜帧模块的相关峰输出，
搜帧模块的使能输出，
搜帧模块的数据输出，
其基本原理就是伪码匹配滤波的原理。
| 系统顶层文件 ——加密调制模块 ————加密子模块，lorenz混沌序列产生模块，组帧模块，并串模块。 ——解密解调模块 ————解密子模块，Lorenz混沌序列产生模块，搜帧模块，串并模块。 |
接口为时钟，复位，搜索到帧头后的使能信号，输入搜索到帧头以后的解密数据，输出并行使能，输出并行信号。
整个系统的综合结果如下所示
仿真结果如下所示：
四、如何下载到硬件
最后你要下载到板子上，你只需配置其管脚即可。
其顶层的文件的管脚为：
| 1 |
i_clk |
系统时钟，就是接到硬件板子上的晶振位置。 |
| 2 |
i_rst |
系统复位，随便接到板子上的key数字按键上。 |
| 3 |
o_signal_enable |
测试并行信号的产生使能信号，不用接板子， |
| 4 |
o_signal |
测试并行信号，这个信号为了验证，你可以接signaltapII上 |
| 5 |
o_enable |
加密模块的使能信号，不用接板子 |
| 6 |
o_serial_dout |
串行输出，接板子上的测试脚或者signaltapII上 |
| 7 |
o_serial_frame |
串行信号组帧输出，接板子上的测试脚或者signaltapII上 |
| 8 |
o_T_signal |
加密输出，这个信号为了验证，你可以接signaltapII上 |
| 9 |
o_dout |
解密输出，可以接signaltapII上 |
| 10 |
o_dout_sign |
解密输出信号的符号判决，接板子上的测试脚或者signaltapII上 |
| 11 |
o_peak |
搜帧模块的相关峰输出，不用接板子 |
| 12 |
o_peak_enable, |
搜帧模块的使能输出，不用接板子 |
| 13 |
o_peak_dout |
搜帧模块的数据输出，接板子上的测试脚或者signaltapII上 |
| 14 |
o_enable2 |
最后串并转化的使能，不用接板子 |
| 15 |
o_voice_dout |
最后串并转化的数据输出，接板子上的测试脚或者signaltapII上 |