1. Problem description:
An improved method for designing chaotic signal generator based on FPGA . First, the Euler algorithm is used to transform the continuous chaotic system into a discrete chaotic system. Secondly, based on the IEEE-754 single-precision floating-point number standard and modular design concept, the Quartus II software is used to design the chaotic signal generator using a combination of VHDL and schematics. Finally, the experiment is carried out on the FPGA experimental system, and the phase diagram of the chaotic attractor and the chaotic signal in the domain are displayed on the oscilloscope. Due to the area optimization method based on the data selector, the floating-point arithmetic module that consumes more logic resources is reused, which greatly reduces the FPGA logic resources occupied by the chaotic signal generator . The experimental results prove the effectiveness and versatility of the method.
2. Part of the program:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY MYDFF IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END MYDFF;
ARCHITECTURE SYN OF mydff IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (31 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(31 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 32
)
PORT MAP (
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
3. Simulation conclusion:
A-007-0004