Original Reference: http: //www.cnblogs.com/jyaray/archive/2011/05/11/2043091.html
Globally defined parameterized
Global definition will bring great convenience to write and simulation, testbench writing process, if there are repeated events incentive, consider these statements to be written in a task. such as:
1.Register its associated bit value may be defined in reg_define.v the global macro.
2. Related path may be defined in define_board.v the global macro.
3. The information display system important variables can be defined in display.v in.
4. Comparison Register associated with the task and error task can be written into the task definition reg_cmp.v.
The parameters define clock cycles, generally defined locally, with the parameter definitions.
Waveform and the corresponding variable data access using the global definitions used `ifdef
1. waveform source file is VCD waveform, but too large, can be used for power analysis.
$ The dumpfile. 1 ( "wave.vcd"); // open the database
2 $ dumpvars ( . 1, top.u1); // scope = top.u1, depth =. 1 . 3 // first parameter represents the depth, is 0 record all depths; second parameter scope, the scope of the current table is omitted. . 4 $ dumpvars; // depth = All = All scope . 5 dumpvars $ ( 0); // depth = All = current scope . 6 $ dumpvars ( . 1 , top.u1); // depth = 1 = top.u1 scope 7 $ dump0ff; // pause recording data changes, signal changes are not written to the library file 8 $ dumpflush; // resume recording
Cadence 2.SHM waveform is to be opened by simvision.
1 $shm_open("waves.shm"); //打开波形数据库 2 $shm_probe(top, "AS"); //set probe on "top" 3 //A -- signals of the specific scrope 4 //S -- Ports of the specified scope and below, excluding library cells 5 //C -- Ports of the specified scope and below, including library cells 6 //AS -- Signals of the specified scope and below, excluding library cells 7 //AC -- Signals of the specified scope and below, including library cells 8 //There is also a M, representing the current scope of the memories, can be used in conjunction with the above, such as "AM" "AMS" "AMC ". ... nothing indicates that the current scope of the ports. Shm_close $ 9 // close the database
3.FSDB Novas waveform is to be opened with nwave.
$ FsdbDumpfile. 1 ( "wave.fsdb"); // open the database 2 $ fsdbDumpvars ( 0, top.u1); // scope = top.u1, depth = 0
4.VPD Synopsys waveform is to be opened with dve.
$ Vcdplusfile. 1 ( "wave.vpd"); // open the database 2 $ vcdpluson ( . 1, top.u1); // scope = top.u1, depth =. 1
Accessing, using the file 5. The variable I / O to operate.
(1) Open the file
1 integer file_id;
2 file_id = fopen("file_path/file_name");
(2) The writing file
1 // $ fmonitor that any change has been recorded 2 $ fmonitor (file_id, " % format_char ", the Parameter); 3 4 // $ fwrite conditions required to trigger recording only 5 $ fwrite (file_id, " % format_char ", the Parameter); 6 7 // $ fdisplay conditions required to trigger recording only 8 $ fdisplay (file_id, " % format_char ", the Parameter);
(3) Read file
1 integer file_id;
2 file_id = $fread("file_path/file_name", "r");
(4) Close the file
$fclose(fjile_id);
(5) the initial value is set by the memory file
$ Readmemh 1 ( " file_name ", memory_name " ); // initialize the data as hexadecimal 2 $ readmemb ( " file_name ", memory_name " ); // initialize to binary data
(6) can also be used to select the variable macro access and use the access time
1 `ifdef SAVE_LROUT
2 start_save = 1’b1;
3 #(10e6) stop_save = 1’b1;
4 `endif 5 xxx = $fopen(“xxx”, “w”); 6 if (start_save && !stop_save) 7 $fwrite(xxx, “%f\n”, x); 8 $fclose;
Incentive systems
1. The normalized data generated by MATLAB, using readmemb / readmemh read Verilog simulation. The same data may be read into MATLAB simulation, to analyze the correlation characteristic.
2. Testbench clock and reset should be imitated on a global level. With non-blocking assignments testbench initialization and reset the clock, with blocking assignments update them.
1 `timescale 1ns/1ns
2 `define PERIOD 5 //100MHz clock 3 initial begin 4 clk <= 0; 5 forever #(`PERIOD) clk = ~clk; 6 end 7 initial begin 8 rst_n <= 0; 9 @(negedge clk) rst_n = 1; 10 end
3. Time scale `timescale: selecting the simulation accuracy and run time balance.
4. bus functional model BFM: means for providing an interface for the simulation model are defined. In other words, the designer is not low-level simulation model of the whole device, it can be a set of timing or agreement to verify.