IC tearing code--digital electronic clock design

Recently, Qiuzhao has encountered this written test question several times, but it is actually relatively simple. The key is the writing method of the counter, so I will make a summary. After that, whether it is the autumn recruitment or the written test of the internship interview, try to get this sub-question.

1. Topic description

Design a digital clock based on f = 100Hz Clock, implement it with Verilog, and generate hours, minutes, and seconds.

analyze:

The premise is to first multiply the frequency of 100hz to a 1hz clock, so that one beat is 1s.

In fact, it is a carry operation, setting the three carry flags of hour, minute, and second, and clearing the second counter when it is full of 60. When the second counter is full of 60, the minute counter is incremented by 1. When the minute is full of 60 and the second is full of 60, the hour is incremented by 1 and the minute is cleared. When the hour counter is full of 24, and the minute is full of 60, and the second is full of 60, the hour is cleared.

2. RTL level description

module clock (
    input clk,
    input rst_n,
    output reg[5:0]hour,
    output reg[5:0]minute,
    output reg[5:0]second
);
// 产生1hz时钟
reg[6:0] clk_cnt;
always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        clk_cnt <= 0;
    else if (clk_cnt == 99)
        clk_cnt <= 0;
    else
        clk_cnt <= clk_cnt + 1;
end
reg clk1;
always @(posedge clk or negedge rst_n) begin
    if(!rst_n)
        clk1 <= 0;
    else if(clk_cnt < 50)
        clk <= 0;
    else    
        clk <= 1;
end
// 秒模块
always @(posedge clk1 or negedge rst_n) begin
    if(!rst_n)
        second <= 0;
    else if(second == 59)
        second <= 0;
    else    
        second <= second + 1;
end
// 分模块
always @(posedge clk1 or negedge rst_n) begin
    if(!rst_n)
        minute <= 0;
    else if((minute == 59)&&(second == 59))
        minute <= 0;
    else if(second == 59)   
        minute <= minute + 1;
end
// 时模块
always @(posedge clk1 or negedge rst_n) begin
    if(!rst_n)
        hour <= 0;
    else if((minute == 59)&&(second == 59)&&(hour == 23))
        hour <= 0;
    else if((minute == 59)&&(second == 59))   
        hour <= hour + 1;
end
endmodule

3. Add setting function

        The hour, minute and second values ​​can be set by 3 buttons. ​​​​​​​​

module clock(
	input clk,
	input rst_n,
	input hour_set,
	input [4:0] hour_set_value,
	
	input minute_set,
	input [5:0] minute_set_value,
	
	input second_set,
	input [5:0] second_set_value,
	
	output reg [4:0] hour,
	output reg [5:0] minute,
	output reg [5:0] second
)

reg clk_1;
reg [6:0] cnt;
// get 1HZ clk
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) 
		cnt <= 0;
	else if(cnt == 99)
		cnt <= 0;
	else
		cnt <= cnt + 1;
end

always@(posedge clk or negedge rst_n) begin
	if(!rst_n) 
		clk_1 <= 0;
	else if(cnt < 50)
		clk_1 <= 0;
	else
		clk_1 <= 1;
end


always@(posedge clk_1 or negedge rst_n) begin
	if(!rst_n) 
		second <= 0;
	else begin
		if(second_set)
			second <= second_set_value;
		else if(second == 59)
			second <= 0;
		else
			second <= second + 1;
	end
end

always@(posedge clk_1 or negedge rst_n) begin
	if(!rst_n) 
		minute <= 0;
	else begin
		if(minute_set)
			minute <= minute_set_value;
		else if( (minute==59) && (second==59) )
			minute <= 0;
		else if(second==59)
			minute <= minute + 1;
	end
end

always@(posedge clk_1 or negedge rst_n) begin
	if(!rst_n)
		hour <= 0;
	else begin
		if(hour_set)
			hour <= hour_set_value;
		else if( (hour==23) && (minute==59) && (second==59) )
			hour <= 0;
		else if((minute==59) && (second==59))
			hour <= hour + 1;
	end
end

endmodule