Digital IC design study notes
8-digit 7-segment digital tube 1
1 原理图
2 Verilog 代码
3 Modelsim仿真
1. Schematic
8-digit digital tube
Internal structure diagram of digital tube
- Digital tubes are divided into common cathode digital tubes and common anode digital tubes; this article uses common anode digital tubes. All the anodes of the led lights inside each digital tube are connected together to give a positive voltage; when the base of the triode is high, the triode is turned on, VCC passes through the resistor, and the triode is loaded to the anode of the led lamp. When the cathode of the led lamp is at a low level, the led lamp is on; when the cathode of the led lamp is at a high level, the led lamp is off.
Since it is impossible to light up a single led light among the 8 digital tubes at the same time, it is realized by dynamic scanning.
Dynamic scanning: divide the operation into different time periods, such as: 8 digital tubes, divided into 8ms, then:
1ms: sel0 = 1, sel1 = 0; sel2 = 0;...sel7 = 0, a=0; LED0 of digital tube 0 is on;
2ms: sel0 = 0, sel1 = 1; sel2 = 0; sel7 = 0, b=0; led1 of digital tube 1 is on;
3ms: sel0 = 0, sel1 = 0; sel2 = 1; sel7 = 0, c=0; led2 of digital tube 2 is on;
…
8ms: sel0 = 0, sel1 = 0; sel2 = 0; sel7 = 1, c=0; led7 of digital tube 7 is on;
switching once every 1ms, Therefore, it needs to divide the frequency to get a 1KHzd clock clk_1k. When the first rising edge of clk_1k comes, the nixie tube 0 is on, and when the second rising edge comes, the nixie tube 1 is on...
–>div - The a, b, c, d, e, f, g segment codes of the control terminal need to be controlled by the display data, and the display data is obtained by decoding the input data. In the first millisecond, a, b, c, d, e, f, g, and h correspond to 1 segment code combination; in the second millisecond, a, b, c, d, e, f, g, and h correspond to 2 segments Code combination... involves the switching of the display content, every millisecond, the display content is different, such as:
digital tube 0, display 1: 1ms, 9ms, 17ms, 25ms, 33ms, 41ms, 49ms, 57ms --> a,b,c,d,e,f,g,h show segment codes corresponding to 1;
nixie tube 1, display 2: 2ms, 10ms, 18ms, 26ms, 34ms, 42ms, 50ms, 58ms -->a,b ,c,d,e,f,g,h present the segment code corresponding to 2;
digital tube 2, display 3: 3ms, 11ms, 19ms, 27ms, 35ms, 43ms, 51ms, 59ms -->a,b,c, d,e,f,g,h show 3 corresponding segment codes;
…
digital tube 7, display 3: 8ms, 16ms, 24ms, 32ms, 40ms, 48ms, 56ms, 64ms -->a,b,c,d, e, f, g, h show the segment codes corresponding to 3;
the status of the segment codes must be switched every 1ms -> the display content switch must be switched every 1ms
. The display data of each digital tube: 4-digit input data data [3:0];
Display data of 8 digital tubes: 8 * 4-bit input data data[3:0] = 32-bit input data data[31:0];
–>MUX8-1 - The selection control terminal of MUX8-1 is the current scanning nixie tube position, sel[7:0], which rotates 1 bit to the left in turn.
–> When shift8 is
low power consumption, control the display of the digital tube or not <=> Control the state of sel, if the value of sel is all 0, the digital tube is completely off;
–>MUX2-1
single digital tube working principle
–> LUT, 4-bit input, 8-bit output
Schematic diagram
Experimental phenomenon:
In Quartus, use the in system source and probes editor to input the data that needs to be displayed on the digital tube, and the digital tube displays the corresponding number.
2 Verilog code
//----top module---------------------------------
module hex8(
input clk,
input rst_n,
input en,
input [31:0] data,
output reg [6:0] seg,
output [7:0] sel
);
reg [14:0] cnt_d;
reg clk_1k;
reg [7:0] sel_reg;
reg [3:0] data_reg;
//----div----------------------------------
always@(posedge clk or negedge rst_n)
if(!rst_n)
cnt_d <= 15'd0;
else if(!en)
cnt_d <= 15'd0;
else if(cnt_d == 15'd24_999)
cnt_d <= 0;
else
cnt_d <= cnt_d + 15'd1;
always@(posedge clk or negedge rst_n)
if(!rst_n)
clk_1k <= 0;
else if(cnt_d == 15'd24_999)
clk_1k <= ~clk_1k;
else
clk_1k <= clk_1k;
//----shift8-------------------------------
always@(posedge clk_1k or negedge rst_n)
if(!rst_n)
sel_reg <= 8'b0000_0001;
else if(sel_reg == 8'b1000_0000)
sel_reg <= 8'b0000_0001;
else
sel_reg <= sel_reg << 1;
//----MUX8-1-------------------------------
always@(*)begin
case(sel_reg)
8'b0000_0001: data_reg <= data[3:0];
8'b0000_0010: data_reg <= data[7:4];
8'b0000_0100: data_reg <= data[11:8];
8'b0000_1000: data_reg <= data[15:12];
8'b0001_0000: data_reg <= data[19:16];
8'b0010_0000: data_reg <= data[23:20];
8'b0100_0000: data_reg <= data[27:24];
8'b1000_0000: data_reg <= data[31:28];
default: data_reg <= 4'd0;
endcase
end
//----LUT-----------------------------------
always@(*)begin
case(data_reg)
4'd0: seg <= 7'b000_0001;
4'd1: seg <= 7'b100_1111;
4'd2: seg <= 7'b001_0010;
4'd3: seg <= 7'b000_0110;
4'd4: seg <= 7'b100_1100;
4'd5: seg <= 7'b010_0100;
4'd6: seg <= 7'b010_0000;
4'd7: seg <= 7'b000_1111;
4'd8: seg <= 7'b000_0000;
4'd9: seg <= 7'b000_0100;
4'd10: seg <= 7'b000_1000;
4'd11: seg <= 7'b110_0000;
4'd12: seg <= 7'b011_0001;
4'd13: seg <= 7'b100_0010;
4'd14: seg <= 7'b011_0000;
4'd15: seg <= 7'b011_1000;
// default: seg <= 000_0000;
endcase
end
//----MUX2-1---------------------------------
assign sel = (en)? sel_reg:8'd0;
endmodule
//-------------------------------------------------
//----testbench--------------------------------
`timescale 1ns/1ns
`define clock_period 20
module tb_hex8;
reg clk;
reg rst_n;
reg en;
reg [31:0] data;
wire [6:0] seg;
wire [7:0] sel;
hex8 uut(
.clk(clk),
.rst_n(rst_n),
.en(en),
.data(data),
.seg(seg),
.sel(sel)
);
initial clk = 1;
always #(`clock_period/2) clk = ~clk;
initial begin
rst_n = 0;
en = 1;
data = 32'h12345678;
#(`clock_period*20);
rst_n = 1;
#(`clock_period*20);
#20000000;
data = 32'h87654321;
#20000000;
data = 32'h89abcdef;
#20000000;
$stop;
end
endmodule
3. Modelsim simulation
The content is derived from the summary of the self-study notes of Xiaomei FPGA ^^
[Note]: Personal study notes, if there are any mistakes, please feel free to enlighten me. This is polite~~~