Digital IC design study notes
Formality
1. 基本特点
2. Reference Design 和Implementation Design
3. container
4. 读入共享技术库
5. 设置Reference Design
6. 设置Implementation Design
7. 保存及恢复所做的设置
8. 运行verify 命令
1. Basic features:
Synopsys Formality is a formal verification tool. You can use it to compare a modified design with its original version, or whether an RTL-level design and its gate-level netlist are functionally consistent.
In IC design, it is usually used to compare different steps of netlist: logic synthesis netlist, floorplannetlist, placement netlist, CTSinserted netlist, P&R netlist, after each step, new logic is added to the netlist, but this new logic The addition of can not change the logic function of the original netlist.
2. Reference Design 和Implementation Design：
Two designs are involved in the formal verification process: one is a standard design whose logic function meets the requirements, which is called Reference Design in Synopsys terminology; the other is a modified design whose logic function has yet to be verified. , Call it Implementation Design
3. container：
We can understand the container as a space used by Formality to read the design, or a "container". Generally, two containers are created to store Reference Design and Implementation Design respectively.
4. Read into the shared technology library:
Before starting the verification process, first read in all the shared technology libraries that will be used
5. Set Reference Design:
- 1) Create a new container;
- 2) Read the entry-level netlist;
- 3) Confirm that the design is Reference Design;
- 4) Link to Reference Design;
6. Set Implementation Design:
- 1) Create a container named impl and read the clk_insert1.v file;
- 2) Confirm the Implementation Design;
- 3) Link the design;
- 4) Set the design as the current design, and then set the test_se port to 0
7. Save and restore settings
8. Run the verify command
Formality will verify the two designs in ref and impl according to the settings made.
Compared with dynamic simulation, the advantages are:
- No need to develop and verify the pattern
- Faster
- 100% coverage
- Purely logical verification, without considering physical and timing information
The disadvantages are:
- Because timing is not considered, it needs to be used with STA tools.
— Reprinted content comes from Zhihu user Amen, Thanks^^: https://zhuanlan.zhihu.com/p/73307269
[Note]: Personal study notes, if there are any mistakes, please feel free to enlighten me. This is polite~~~