First, based on the ASIC design flow standcell
Standcell library is the so-called standard cell library, mainly refers to a digital circuit, an inverter, a NAND gate, NOR gate, XOR gate, the basic components of the Schmitt trigger or the like.
Design process are:
arithmetic model (C / C ++ / Matlab) ---> RTL HDL VHDL / Verilog ---> NetlistVerilog ---> Layout GDSII ---> Tape-Out
standcell library包含：NetlistVerilog和Layout GDSII
RTL HDL VHDL/Verilog--->NetlistVerilog 逻辑综合工具根据基本单元库的功能-时序模型，将行为级代码翻译成具体的电路实现结构
Netlist Verilog--->Layout GDSII 布局布线工具根据基本单元库的时序-几何模型，将电路单元布局布线成实际电路板图
Layout GDSII--->Tape-Out 对功能，时序，制造参数进行检查Second, the whole process of digital IC design
Marketing request -> Architecture Spec .--> Arch / Algorithm Emulation -> Design Spec .--> RTL Coding -> IP Level RTL coding -> IP Level RTL simulation -> Unit / chip Level RTL simulation- -> logic synthesis (logic synthesis) -> formal verification -> the STA (static timing analysis) -> DFT (design for test ) -> PR layout generation, automatic placement and routing -> clock tree insertion -> DRC / LVS -> Post layout STA -> GDSII generated
in the above process, engineers duty and tools can be summarized in the following table
| Process | engineer | jobs | tool |
|---|---|---|---|
| Marketing request | - | - | - |
| Architecture Spec. | Architecture engineer | Top atchitect,Project function spec | - |
| Arch/Algorithm Emulation | Algorithm Engineer | - | C/C++/Matlab |
| Design Spec. | - | Design spec example | - |
| RTL Coding | RTL design engineer | - | Using VHDL / Verilog / System Verilog realization |
| IP Level RTL coding | - | - | - |
| IP Level RTL coding | IP level verification engineer | IP level verification | Make file; simulation tool, Cadence: Incisive, Synopsys: VCS, Mentor: QuestaSim |
| Unit/chip Level RTL simulation | Integrate engineer | Unit/chip level verification(full chip verification engineer) | - |
| Logic Synthesis | ASIC Design Engineer | Gate Level verification | Logic synthesis tools, Cadence: Genus, Synopsys: Design Compiler |
| Formal verification | ASIC Front-End Design Engineer | - | Formal verification tools, Cadence: Conformal, Synopsys: Formality |
| STA (static timing analysis) | ASIC Front-End Design Engineer | TCL Script | Static timing analysis tool, Cadence: Tempus, Synopsys: Prme Time |
| DFT(design for test) | DFT engineer | Insert a test scan chain link | - |
| PR layout generation, automatic placement and routing | Physical Design Engineer | - | Automatic routing tool, Cadence: Innovus, Synopsys: IC Compiler |
| Clock tree insertion | - | - | - |
| DRC/LVS | - | - | Physical verification tool, Cadence: Diva / dracula, Synopsys: Hercules, Mentor: Calibre |
| Post layout STA | - | - | - |
| Generate the final GDSII | - | - | - |
| Tap-Out | - | - | - |
逻辑综合就是把设计实现的RTL代码映射到特定的工艺库，输出成门级网表Netlist
从功能上(STA是时序上)对综合后的网表进行验证。常用的就是等价性检查(Equivalence Check),以功能验证后的HDL设计为参考，对综合后的网表功能，他们是否在功能上存在等价性。
静态时序分析，主要在时序上对电路进行验证，检查电路是否存在建立时间，保持时间的违例Front-end design and back-end design
前端设计（RTL to Netlist）
RTL(Register Transfer Level)利用引荐描叙语言对电路以寄存器之间的传输进行描述
逻辑综合：将RTL级设计中所得的程序代码翻译成实际电路的各种元器件以及他们的连接关系，用一张图来表示成为网表(Netlist)
STA(static timing analysis,静态时序分析)，套用特定的时序模型，针对电路分析是否违反给定的时序限制
后端设计（Netlist to Layout）
APR(自动布局布线)-->Extract RC（提取延时信息）-->DRC(设计规则检查)-->LVS（版图电路一致性检查）VSLI design process
